search for: gettargetnodenam

...Machine Node #65434>>"). Can I use "machine nodes" and "normal nodes" > when lowering a specific instruction within the TargetLowering? Usually, when I see this type of error in the X86 target, I use the following function to narrow down the search: > /// getTargetNodeName - This method returns the name of a target specific > /// DAG node. > virtual const char *getTargetNodeName(unsigned Opcode) const; If I'm not mistaken, the normal dump method returns names for ISD Opcodes and not for target specific opcodes, in my case X86ISD Opcodes. -----------...

Hi LLVM-Folks, as mentioned in an earlier post (http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-July/051677.html) I am currently working on a Back-End for the TriCore processor. Currently, I am struggling as LLVM could not select zext and load, for instance, so some of the testcases in test/CodeGen/Generic are not successfully compiled by my back-end. Furthermore, I am completely puzzled by the

I'm still relatively new to llvm, good to know these errors are from CodeGen. On 03/03/19 10:49 AM, Tim Northover wrote: > On Sat, 2 Mar 2019 at 21:00, preejackie via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> Could you please explain how you are using this? like commands >> >> When I run this IR in opt, it doesn't throw any errors. > The error

Hi, I am creating a new backend for a custom microcontroller. In order to create the backend I am modifying from Mips backend. My architecture has a store instruction with direct address mode. It accepts two arguments: source register and address (immediate). This instruction is not available in Mips, but it is in Hexagon, so I copied from Hexagon the following, adapting it to my registers: -

...::i32, Custom); + setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); + if (Subtarget->is64Bit()) { setOperationAction(ISD::ADDC, MVT::i64, Custom); setOperationAction(ISD::ADDE, MVT::i64, Custom); *************** *** 1808,1835 **** const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { switch ((SPISD::NodeType)Opcode) { ! case SPISD::FIRST_NUMBER: break; ! case SPISD::CMPICC: return "SPISD::CMPICC"; ! case SPISD::CMPFCC: return "SPISD::CMPFCC"; ! case SPISD::BRICC: return "SPISD::BRICC"; ! case SPI...

...t; diff --git a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp > index 0820898..6c5b1ed 100644 > --- a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp > +++ b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp > @@ -2782,6 +2782,7 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const { > NODE_NAME_CASE(INTERP_P2) > NODE_NAME_CASE(STORE_MSKOR) > NODE_NAME_CASE(TBUFFER_STORE_FORMAT) > + NODE_NAME_CASE(CMP_SWAP) > case AMDGPUISD::LAST_AMDGPU_ISD_NUMBER: break; > } > return nullptr; > diff --git a/lib/Target/AMDGPU/...

Hi Tom, Matt, I'm working on a project that needs few coherent atomic operations (HSA mode: load, store, compare-and-swap) for std::atomic_uint in HCC. the attached patch implements atomic compare and swap for SI+ (untested). I tried to stay within what was available, but there are few issues that I was unsure how to address: 1.) it currently uses v2i32 for both input and output. This

...tLowering::PPCTargetLowering(PPCTargetMachine &TM) - : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()), - PPCAtomicLabelIndex(0) { + : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) { setPow2DivIsCheap(); @@ -378,45 +377,47 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { switch (Opcode) { default: return 0; - case PPCISD::FSEL: return "PPCISD::FSEL"; - case PPCISD::FCFID: return "PPCISD::FCFID"; - case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; - case PPCISD::FCTIWZ: retu...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...tLowering::PPCTargetLowering(PPCTargetMachine &TM) - : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()), - PPCAtomicLabelIndex(0) { + : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) { setPow2DivIsCheap(); @@ -378,45 +377,47 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { switch (Opcode) { default: return 0; - case PPCISD::FSEL: return "PPCISD::FSEL"; - case PPCISD::FCFID: return "PPCISD::FCFID"; - case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; - case PPCISD::FCTIWZ: retu...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:

You need to insert new basic blocks and update CFG to accomplish this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See

...tLowering::PPCTargetLowering(PPCTargetMachine &TM) - : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()), - PPCAtomicLabelIndex(0) { + : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) { setPow2DivIsCheap(); @@ -378,45 +377,47 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { switch (Opcode) { default: return 0; - case PPCISD::FSEL: return "PPCISD::FSEL"; - case PPCISD::FCFID: return "PPCISD::FCFID"; - case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; - case PPCISD::FCTIWZ: retu...

Would it be acceptable to change MachineInstr::getRegInfo from private to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter? Cheers, Gary Evan Cheng wrote: > Look for createVirtualRegister. These are examples in > PPCISelLowering.cpp. > > Evan > On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > > > Hi Evan, > > > > Evan Cheng wrote:

Chris Lattner wrote: > On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > > $label), > > "cmpw $rA, $rB\n\tbne- La${label}_exit", > > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > > $label)]>; > > } > > > > ...and

...tLowering::PPCTargetLowering(PPCTargetMachine &TM) - : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()), - PPCAtomicLabelIndex(0) { + : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) { setPow2DivIsCheap(); @@ -378,45 +377,47 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { switch (Opcode) { default: return 0; - case PPCISD::FSEL: return "PPCISD::FSEL"; - case PPCISD::FCFID: return "PPCISD::FCFID"; - case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; - case PPCISD::FCTIWZ: retu...

...terInfo & MRI, > + const TargetInstrInfo * TII, unsigned reg) const > +{ > + AMDGPU::utilAddLiveIn(MF, MRI, TII, reg, MI->getOperand(0).getReg()); > +} > + > +#define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node; > + > +const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const > +{ > + switch (Opcode) { > + default: return AMDILTargetLowering::getTargetNodeName(Opcode); > + > + NODE_NAME_CASE(FRACT) > + NODE_NAME_CASE(FMAX) > + NODE_NAME_CASE(SMAX) > + NODE_NAME_CASE(UMAX) > + NODE_NAME_CASE(FMIN) > + NODE_NAM...