search for: gettargetnode

Displaying 14 results from an estimated 14 matches for "gettargetnode".

2008 Sep 19
2
[LLVMdev] Custom Opcodes versus built-in opcodes
...to my backend. These opcodes are then used to emit a custom set of instructions into the MachineBasicBlock. I've been able to get one to work correctly, however, I've ran into an issue where my second one is being confused as a FRAMEADDR opcode instead of my opcode. Make sure to use DAG.getTargetNode() with custom opcodes. "target" nodes are encoded with an implicit delta added to their enum value. Is this documented anywhere that getTargetNode is the preferred method to use in a Custom Lowering function? Even the other backends use getNode in their lowering functions with custom...
2008 Sep 19
0
[LLVMdev] Custom Opcodes versus built-in opcodes
On Sep 19, 2008, at 11:35 AM, Villmow, Micah wrote: > Make sure to use DAG.getTargetNode() with custom opcodes. "target" > nodes are encoded with an implicit delta added to their enum value. > > Is this documented anywhere that getTargetNode is the preferred > method to use in a Custom Lowering function? Even the other backends > use getNode in their low...
2008 Oct 20
2
[LLVMdev] TableGen Hacking Help
...ory operations. It generates two MOVSDs and a SHUFPD just fine but it produces two extra MOVSD instructions. As far as I can understand things, the problem is that the two MOVSD instructions are generated by a recursive call to EmitResultCode. Thus isRoot is false and the result of the call to getTargetNode is not passed to ReplaceUses. Then when we pop back up and generate the SHUFPD we call SelectNodeTo which only transforms the immediate node (the vector_shuffle). It doesn't recurse to replace child nodes. I tried hacking tblgen to call getTargetNode / ReplaceUses if any node in the patt...
2008 Sep 12
3
[LLVMdev] Difficulty with reusing DAG nodes.
...OHI: case ISD::UMUL_LOHI: { SDValue Op1 = Node->getOperand(0); SDValue Op2 = Node->getOperand(1); AddToISelQueue(Op1); AddToISelQueue(Op2); unsigned Op; Op = (Opcode == ISD::UMUL_LOHI ? Nios2::MULxu : Nios2::MULx); SDNode *Hi = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2); SDNode *Lo = CurDAG->getTargetNode(Nios2::MUL, MVT::Flag, Op1, Op2); if (!N.getValue(0).use_empty()) ReplaceUses(N.getValue(0), SDValue(Lo,0)); if (!N.getValue(1).use_empty()) ReplaceUses(N.getValue(1), SDValue(Hi,0)); retur...
2009 Apr 13
1
[LLVMdev] Porting LLVM backend is no fun yet
Dan Gohman wrote: > There certainly are wishlist items for TableGen and TableGen-based > instruction descriptions, though I don't know of an official list. > Offhand, > a few things that come to mind are the ability to handle nodes with > multiple results, Is there an official workaround, BTW? - Volodya
2008 Sep 19
0
[LLVMdev] Custom Opcodes versus built-in opcodes
...ese opcodes are then used > to emit a custom set of instructions into the MachineBasicBlock. > I’ve been able to get one to work correctly, however, I’ve ran into > an issue where my second one is being confused as a FRAMEADDR opcode > instead of my opcode. Make sure to use DAG.getTargetNode() with custom opcodes. "target" nodes are encoded with an implicit delta added to their enum value. -Chris -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20080919/6530bb94/attachment.html>
2008 Oct 20
0
[LLVMdev] TableGen Hacking Help
On Mon, 2008-10-20 at 11:49 -0500, David Greene wrote: > I tried hacking tblgen to call getTargetNode / ReplaceUses if any node in the > pattern has a chain by changing this line in tblgen: > > bool InputHasChain = isRoot && > NodeHasProperty(Pattern, SDNPHasChain, CGP); > > to call PatternHasProperty instead. This does cause tblgen to emit > getTarge...
2008 Sep 11
0
[LLVMdev] Tail-calling
On Thu, Sep 11, 2008 at 4:31 PM, Arnold Schwaighofer <arnold.schwaighofer at gmail.com> wrote: > Tail calls through function pointers should work.If not please send a testcase. > > I just added the two examples from the bug (1392) that calls for true > tail call support. They work on my machine (-tailcallopt needs to be > enabled) ;) > > That would be commit 56127. >
2008 Sep 18
4
[LLVMdev] Custom Opcodes versus built-in opcodes
I am using lowering instructions and using custom opcodes that I can more easily directly map to my backend. These opcodes are then used to emit a custom set of instructions into the MachineBasicBlock. I've been able to get one to work correctly, however, I've ran into an issue where my second one is being confused as a FRAMEADDR opcode instead of my opcode. DValue
2008 Sep 11
3
[LLVMdev] Tail-calling
Tail calls through function pointers should work.If not please send a testcase. I just added the two examples from the bug (1392) that calls for true tail call support. They work on my machine (-tailcallopt needs to be enabled) ;) That would be commit 56127. regards On Thu, Sep 11, 2008 at 11:21 PM, Evan Cheng <evan.cheng at apple.com> wrote: > Arnold implemented tail call. We
2007 Jan 14
0
[LLVMdev] Inserting an assembly instruction in the calling sequence of the powerpc target
On Fri, 12 Jan 2007, Nicolas Geoffray wrote: > I'm currently implementing a linux/ppc target in llvm. The abis between cool > Darwin/ppc and linux/ppc are different and I'm running into problems > with vararg calls. ok > Before a variadic method is called, an extra instruction must be > executed (which is creqv 6, 6, 6). This instruction is not necessary in >
2007 Jan 12
2
[LLVMdev] Inserting an assembly instruction in the calling sequence of the powerpc target
Hi all, I'm currently implementing a linux/ppc target in llvm. The abis between Darwin/ppc and linux/ppc are different and I'm running into problems with vararg calls. Before a variadic method is called, an extra instruction must be executed (which is creqv 6, 6, 6). This instruction is not necessary in Darwin/ppc. I looked into the PowerPC target implementation and the code generation
2008 Nov 06
0
[LLVMdev] Multi-instruction patterns, tablegen and chains
On Nov 4, 2008, at 12:12 AM, Matthijs Kooijman wrote: > Hi Dan, > >> Having tblgen pretend that the MOVE isn't the root seems a bit >> counter-intuitive though. > I didn't really mean making RD the root, but rather telling tablegen > that RD > is the "primary" node, corresponding to the input pattern. This > would allow > the properties of
2008 Nov 04
2
[LLVMdev] Multi-instruction patterns, tablegen and chains
Hi Dan, > Having tblgen pretend that the MOVE isn't the root seems a bit > counter-intuitive though. I didn't really mean making RD the root, but rather telling tablegen that RD is the "primary" node, corresponding to the input pattern. This would allow the properties of the input rd SDNode be properly transferred to the output RD node instead of the MOVE node. I doubt