Displaying 4 results from an estimated 4 matches for "getsubregisterforindex".
2007 Apr 24
2
[LLVMdev] Register based vector insert/extract
...onstraint would need to be
enforced was during the register rewriting pass.
My first productive thoughts were to create a subclass of SDOperand
(SDSubOperand) that Lowering could use to communicate the target
specific subregister index. The other thought was to have something
akin to "getSubRegisterForIndex()" in MRegisterInfo, which would
return a sub register of the correct type at the specified index in a
target dependent way. I'm not familiar with the register rewriting
pass, so I'm not sure what data structures it needs/has access to.
--
Christopher Lamb
2007 Apr 24
0
[LLVMdev] Register based vector insert/extract
...to be
> enforced was during the register rewriting pass.
>
> My first productive thoughts were to create a subclass of SDOperand
> (SDSubOperand) that Lowering could use to communicate the target
> specific subregister index. The other thought was to have something
> akin to "getSubRegisterForIndex()" in MRegisterInfo, which would
> return a sub register of the correct type at the specified index in a
> target dependent way. I'm not familiar with the register rewriting
> pass, so I'm not sure what data structures it needs/has access to.
Yes, we need those. I think thes...
2007 Apr 24
0
[LLVMdev] Register based vector insert/extract
On Apr 23, 2007, at 4:07 PM, Christopher Lamb wrote:
> Thanks for the detailed response.
>
> On Apr 23, 2007, at 4:22 PM, Chris Lattner wrote:
>
>> Right. Evan is currently focusing on getting the late stages of
>> the code
>> generator (e.g. livevars) to be able to understand arbitrary machine
>> instrs in the face of physreg subregs. This lays the
2007 Apr 23
2
[LLVMdev] Register based vector insert/extract
Thanks for the detailed response.
On Apr 23, 2007, at 4:22 PM, Chris Lattner wrote:
> Right. Evan is currently focusing on getting the late stages of
> the code
> generator (e.g. livevars) to be able to understand arbitrary machine
> instrs in the face of physreg subregs. This lays the groundwork for
> handling vreg subregs, but won't solve it directly.
Is the work Evan