search for: getsubregist

There's an assert at line 192, lib/CodeGen/RegisterScavenging.cpp that appears to get tripped on targets that don't have subregisters defined: bool SubUsed = false; for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); unsigned SubReg = *SubRegs; ++SubRegs) if (isUsed(SubReg)) { SubUsed = true; break; } assert(SubUsed && "Using an undefined register!"); CellSPU does not define any subregisters; consequently, SubUsed will...

...ichel <scooter.phd at gmail.com> wrote: > There's an assert at line 192, lib/CodeGen/RegisterScavenging.cpp that > appears to get tripped on targets that don't have subregisters defined: > > bool SubUsed = false; > for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); > unsigned SubReg = *SubRegs; ++SubRegs) > if (isUsed(SubReg)) { > SubUsed = true; > break; > } > assert(SubUsed && "Using an undefined register!"); > > CellSPU does not define any su...

...26: [458,5168:0 [0]) > %reg15: [938,942:1 [0]) > > My assumption was that after MergeInClobberRanges that %reg15 > would contain [458,5168:0 [0]). But it doesn't. So this is the call site? // Update the liveintervals of sub-registers. for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS) li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt, li_- >getVNInfoAllocator()); Can you take a look at MergeInClobberRanges() to see what is going on? Otherwise, please file a bug with a test case...

...neBasicBlock::iterator I) { unsigned DstReg = I->getOperand(0).getReg(); unsigned SrcReg = I->getOperand(1).getReg(); const MCInstrDesc& Dmfc1Tdd = TII->get(MIPS::DMFC1); DebugLoc dl = I->getDebugLoc(); const uint16_t* SubReg = TM.getRegisterInfo()->getSubRegisters(SrcReg); BuildMI(MBB, I, dl, Dmfc1Tdd, DstReg).addReg(*SubReg); } Finally, I want to add the rule to ISelLowering to actually use these rules. Under the CCValAssign::Full case in the LowerCall function, here is the old code: SDValue Lo = DAG.getNode(MIPSISD::ExtractElement...

...v4r0 with subregisters {r0, r1, r2, r3} and a > DAG that looks like > > load v4si <- extract_element 2 <- add -> load i32 > > I'd like to be able to generate > > load v4r0 > load r10 > add r11, r10, r2 <== subregister 2 of v4r0 I see that Evan has added getSubRegisters()/getSuperRegisters() to MRegisterInfo. This is what's needed in order to implement the register allocation constraint, but there's no way yet to pass the constraint through the operands from the DAG. There would need to be some way to specify that the SDOperand is referencing a...

...unsigned DstReg = I->getOperand(0).getReg(); > unsigned SrcReg = I->getOperand(1).getReg(); > const MCInstrDesc& Dmfc1Tdd = TII->get(MIPS::DMFC1); > > DebugLoc dl = I->getDebugLoc(); > const uint16_t* SubReg = > TM.getRegisterInfo()->getSubRegisters(SrcReg); > > BuildMI(MBB, I, dl, Dmfc1Tdd, DstReg).addReg(*SubReg); > } > > If I understand correctly what you are trying to do, DMFC1 is supposed to read a f64 register and copy it to a pair of i32 registers. This code doesn't seem to be doing that. Why do you need...

I am going to remove these functions from MCRegisterInfo: getSubRegisters() getSuperRegisters() getOverlaps() getAliasSet() They have been replaced with iterator classes, also defined in MCRegisterInfo.h: MCSubRegIterator MCSuperRegIterator MCRegAliasIterator The tree has lots of examples of how to use all three. /jakob

On Apr 23, 2007, at 1:17 PM, Christopher Lamb wrote: > > On Apr 23, 2007, at 12:31 PM, Chris Lattner wrote: > >> On Mon, 23 Apr 2007, Christopher Lamb wrote: >>> How can one let the back end know how to insert and extract >>> elements of >>> a vector through sub-register copies? I'm at a loss how to do >>> this... >> >> You

On Wednesday 20 February 2008 07:00:28 pm Evan Cheng wrote: > > In other words, after coalescing, should it be the case that > > subregister > > intervals contain at least all of the range information that was > > contained > > in any eliminated intervals when those eliminated intervals were > > coalesced > > to the subregister's superregister? >

...t gmail.com>wrote: > >> There's an assert at line 192, lib/CodeGen/RegisterScavenging.cpp that >> appears to get tripped on targets that don't have subregisters defined: >> >> bool SubUsed = false; >> for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); >> unsigned SubReg = *SubRegs; ++SubRegs) >> if (isUsed(SubReg)) { >> SubUsed = true; >> break; >> } >> assert(SubUsed && "Using an undefined register!"); >> >&gt...

...s-is. Just curious. > > My assumption was that after MergeInClobberRanges that %reg15 > > would contain [458,5168:0 [0]). But it doesn't. > > So this is the call site? > > // Update the liveintervals of sub-registers. > for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS) > li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt, > li_- Yep. > >getVNInfoAllocator()); > > Can you take a look at MergeInClobberRanges() to see what is going on? > Otherwise, p...

On Apr 23, 2007, at 12:31 PM, Chris Lattner wrote: > On Mon, 23 Apr 2007, Christopher Lamb wrote: >> How can one let the back end know how to insert and extract >> elements of >> a vector through sub-register copies? I'm at a loss how to do this... > > You probably want to custom lower the insertelement/extractelement > operations for the cases you support.

On Feb 20, 2008, at 12:25 PM, David Greene wrote: > On Wednesday 20 February 2008 14:14, David Greene wrote: > >> I discovered this through an assert I put into some of my own >> code. I want >> to know if that assert is bogus or if there's a bug here. > > A little more information: the assert checks that after coalescing > two nodes, > all subregister

...register. If not, it uses an asmprinter hack to print this as a copy instruction. This is horrible, and doesn't produce good code. OTOH, before Evan improved this, we always copied into AX and out of AL for each i16->i8 truncate, which was much worse :) > I see that Evan has added getSubRegisters()/getSuperRegisters() to > MRegisterInfo. This is what's needed in order to implement the > register allocation constraint, but there's no way yet to pass the > constraint through the operands from the DAG. There would need to be > some way to specify that the SDOperand is re...