Displaying 4 results from an estimated 4 matches for "getsubregindexlanemask".
2013 May 16
1
[LLVMdev] Combining physical registers
...is my understanding that register lane masks are not exact in a sense that they will tell me if two register lanes alias, but not necessarily if a set of masks adds up to a full register. Is this correct?
That’s right.
Would this TRI function solve your problem?
/// The lane masks returned by getSubRegIndexLaneMask() above can only be
/// used to determine if sub-registers overlap - they can't be used to
/// determine if a set of sub-registers completely cover another
/// sub-register.
///
/// The X86 general purpose registers have two lanes corresponding to the
/// sub_8bit and sub_8bit_hi su...
2013 May 16
0
[LLVMdev] Combining physical registers
On 5/16/2013 11:17 AM, Jakob Stoklund Olesen wrote:
>
> Would this TRI function solve your problem?
>[...]
> ///
> /// Covering = getCoveringLanes();
> /// MaskA = getSubRegIndexLaneMask(SubA);
> /// MaskB = getSubRegIndexLaneMask(SubB);
> ///
> /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
> /// SubB.
> unsigned getCoveringLanes() const { return CoveringLanes; }
Yes, this would solve my problem. I'm assu...
2013 May 16
2
[LLVMdev] Combining physical registers
The function TII::canCombineSubRegIndices has been gone for a while now,
and I was wondering if there is a target-independent way of determining
if a certain set of physical registers "adds up" to a larger register.
For example, on X86, AL and AH together form AX. On Hexagon, R0 and R1
are D0.
The context here is an attempt to coalesce multiple loads/stores into
fewer loads/stores
2012 Oct 29
1
[LLVMdev] Data flow/liveness in register pairs
Hello,
Consider this code (this is all after register allocation):
R0<def> = ... R0 // Set lower half (based on the previous value)
R1<def> = ... // Set upper half
... = R0_R1 // Use the pair
It is my understanding that the use of the whole pair will need to have
some sort of a reaching def, i.e. the code will need at least those flags:
R0<def> =