Displaying 20 results from an estimated 33 matches for "getsubreg".
2013 Apr 18
4
[LLVMdev] MachineOperand SubReg
I'm working on the post-regalloc dataflow engine I mentioned yesterday.
Currently I only need to track register operands.
A MachineOperand has both a getReg() and a getSubReg() interface. For a
physical register operand, is getReg() guaranteed to be the "most super"
register with getSubReg() providing the specific subregister information
for the operand? If so then for my current purposes it seems I don't
need to worry about subregisters at all.
For rea...
2013 Apr 19
2
[LLVMdev] MachineOperand SubReg
Jakob Stoklund Olesen <stoklund at 2pi.dk> writes:
>> A MachineOperand has both a getReg() and a getSubReg() interface.
>> For a physical register operand, is getReg() guaranteed to be the
>> "most super" register with getSubReg() providing the specific
>> subregister information for the operand? If so then for my current
>> purposes it seems I don't need to worry...
2013 Apr 18
0
[LLVMdev] MachineOperand SubReg
On Apr 18, 2013, at 9:45 AM, dag at cray.com wrote:
> I'm working on the post-regalloc dataflow engine I mentioned yesterday.
> Currently I only need to track register operands.
>
> A MachineOperand has both a getReg() and a getSubReg() interface. For a
> physical register operand, is getReg() guaranteed to be the "most super"
> register with getSubReg() providing the specific subregister information
> for the operand? If so then for my current purposes it seems I don't
> need to worry about subregist...
2013 Apr 19
0
[LLVMdev] MachineOperand SubReg
On Apr 19, 2013, at 7:18 AM, <dag at cray.com> wrote:
> Jakob Stoklund Olesen <stoklund at 2pi.dk> writes:
>
>>> A MachineOperand has both a getReg() and a getSubReg() interface.
>>> For a physical register operand, is getReg() guaranteed to be the
>>> "most super" register with getSubReg() providing the specific
>>> subregister information for the operand? If so then for my current
>>> purposes it seems I don'...
2011 Oct 12
1
[LLVMdev] Problem in TwoAddressInstructionPass::runOnMachineFunction regarding subRegs
...ation for me but I'm all new to
this so I'm not sure how it's supposed to work. I'm running on 2.9.
Any comments?
@@ -1172,12 +1172,20 @@ bool
TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg();
TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, *TRI);
ReMatRegs.set(TargetRegisterInfo::virtReg2Index(regB));
++NumReMats;
} else {
- BuildMI(*mbbi, mi, mi->getDebugLoc(),
TII->get(TargetOpcode::COPY),
-...
2014 Aug 15
2
[LLVMdev] Help with definition of subregisters; spill, rematerialization and implicit uses
...ading the register value from before the current
/// instruction or bundle. Internal bundle reads are not included.
bool readsReg() const {
assert(isReg() && "Wrong MachineOperand accessor");
return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
}
I don't get why we automatically should get an implicit use just
because we are writing a subreg.
Since Reg5:lo16 is defined with
Reg5:lo16<def> = Reg1
isUndef() will return false and getSubReg() true, and thus readsReg()
true and the reload is inserted.
Then we...
2010 Jul 20
2
[LLVMdev] Spilling multi-word virtual registers
...ructions: one for each sub-register.
For quite a while now, my implementation of loadRegFromStackSlot() and
storeRegToStackSlot() has assumed that it would only receive physical
registers, which makes it fairly straight-forward. They generate three
memory instructions, calling TargetRegisterInfo::getSubReg() to get the
sub-register operand for each of them.
So it was a rude awakening when a test program resulted in a _virtual_
register being passed into loadRegFromStackSlot() (via
LiveIntervals::tryFoldMemoryOperand() if it matters). Obviously I need
to make some changes. But what?
A couple options...
2012 Oct 29
3
[LLVMdev] [llvm-commits] [llvm] r162770 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp
...ug 28 13:05:48 2012
> @@ -208,8 +208,8 @@
> hash_code llvm::hash_value(const MachineOperand &MO) {
> switch (MO.getType()) {
> case MachineOperand::MO_Register:
> - return hash_combine(MO.getType(), MO.getTargetFlags(),
> MO.getReg(),
> - MO.getSubReg(), MO.isDef());
> + // Register operands don't have target flags.
> + return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(),
> + MO.isDef());
> case MachineOperand::MO_Immediate:
> return hash_combine(MO.getType(), MO.getTargetFlags(),
> MO.getImm());
>...
2007 May 31
4
[LLVMdev] Advice on a VStudio specific patch
Here are the two problem areas:
RegisterInfoEmitter.cpp
// Emit the subregister + index mapping function based on the
information
// calculated above.
OS << "unsigned " << ClassName
<< "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
<< " switch (RegNo) {\n"
<< " default: abort(); break;\n";
...
OS << " };\n";
OS << " return 0; // Visual Studio 2005 does not respect the
no-return semantics of abort\n"...
2010 Jul 20
0
[LLVMdev] Spilling multi-word virtual registers
...ub-register.
>
> For quite a while now, my implementation of loadRegFromStackSlot() and
> storeRegToStackSlot() has assumed that it would only receive physical
> registers, which makes it fairly straight-forward. They generate three
> memory instructions, calling TargetRegisterInfo::getSubReg() to get the
> sub-register operand for each of them.
>
> So it was a rude awakening when a test program resulted in a _virtual_
> register being passed into loadRegFromStackSlot() (via
> LiveIntervals::tryFoldMemoryOperand() if it matters). Obviously I need
> to make some change...
2007 Jun 01
0
[LLVMdev] Advice on a VStudio specific patch
...t adobe.com> wrote:
> Here are the two problem areas:
>
> RegisterInfoEmitter.cpp
>
> // Emit the subregister + index mapping function based on the
> information
> // calculated above.
> OS << "unsigned " << ClassName
> << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
> << " switch (RegNo) {\n"
> << " default: abort(); break;\n";
> ...
> OS << " };\n";
> OS << " return 0; // Visual Studio 2005 does not respect the
> no-re...
2012 Oct 29
0
[LLVMdev] [llvm-commits] [llvm] r162770 - in /llvm/trunk: include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp
...@@ -208,8 +208,8 @@
>> hash_code llvm::hash_value(const MachineOperand &MO) {
>> switch (MO.getType()) {
>> case MachineOperand::MO_Register:
>> - return hash_combine(MO.getType(), MO.getTargetFlags(),
>> MO.getReg(),
>> - MO.getSubReg(), MO.isDef());
>> + // Register operands don't have target flags.
>> + return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(),
>> + MO.isDef());
>> case MachineOperand::MO_Immediate:
>> return hash_combine(MO.getType(), MO.getTargetFlags(),
&g...
2012 Nov 05
0
[LLVMdev] problem trying to write an LLVM register-allocation pass
...ning in the development branch, then I'll add some sort of
verification to catch it.
The VirtRegMap::rewrite() method sidesteps this issue by rewriting physreg
operands to remove the subreg field. The code for this is in
VirtRegMap.cpp, around line 165. In short:
PhysReg = MO.getReg();
if (MO.getSubReg() != 0) {
PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
MO.setSubReg(0);
}
MO.setReg(PhysReg);
Adding this code to Gcra fixes the assembly issue for me. I've attached my
updated copy. Hope this helps.
Cheers,
Lang.
On Sun, Nov 4, 2012 at 2:08 PM, Susan Horwitz <horwitz at cs....
2012 Jul 26
2
[LLVMdev] X86 sub_ss and sub_sd sub-register indexes
...only mentioned here:
let CompositeIndices = [(sub_ss), (sub_sd)] in {
def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>;
def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>;
...
This secret syntax means that the indexes are idempotent:
getSubReg(YMM0, sub_ss) --> XMM0
getSubReg(XMM0, sub_ss) --> XMM0
They are supposed to represent the 32-bit and 64-bit low parts of the xmm registers, but since we don't define explicit registers for those sub-registers, we are left with idempotent sub-register indexes.
We have three different...
2012 Nov 08
2
[LLVMdev] problem trying to write an LLVM register-allocation pass
...>>>
>>> The VirtRegMap::rewrite() method sidesteps this issue by rewriting
>>> physreg operands to remove the subreg field. The code for this is in
>>> VirtRegMap.cpp, around line 165. In short:
>>>
>>> PhysReg = MO.getReg();
>>> if (MO.getSubReg() != 0) {
>>> PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
>>> MO.setSubReg(0);
>>> }
>>> MO.setReg(PhysReg);
>>>
>>> Adding this code to Gcra fixes the assembly issue for me. I've attached
>>> my updated copy. Hope t...
2012 Nov 09
0
[LLVMdev] problem trying to write an LLVM register-allocation pass
...rewrite() method sidesteps this issue by
> rewriting
> physreg operands to remove the subreg field. The code for
> this is in
> VirtRegMap.cpp, around line 165. In short:
>
> PhysReg = MO.getReg();
> if (MO.getSubReg() != 0) {
> PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
> MO.setSubReg(0);
> }
> MO.setReg(PhysReg);
>
> Adding this code to Gcra fixes the assembly issue for me.
> I've attached
>...
2012 Nov 05
2
[LLVMdev] problem trying to write an LLVM register-allocation pass
...hen I'll add some sort of verification to catch it.
>
> The VirtRegMap::rewrite() method sidesteps this issue by rewriting
> physreg operands to remove the subreg field. The code for this is in
> VirtRegMap.cpp, around line 165. In short:
>
> PhysReg = MO.getReg();
> if (MO.getSubReg() != 0) {
> PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
> MO.setSubReg(0);
> }
> MO.setReg(PhysReg);
>
> Adding this code to Gcra fixes the assembly issue for me. I've attached
> my updated copy. Hope this helps.
>
> Cheers,
> Lang.
>
>
> O...
2012 Nov 07
0
[LLVMdev] problem trying to write an LLVM register-allocation pass
...f verification to catch it.
>>
>> The VirtRegMap::rewrite() method sidesteps this issue by rewriting
>> physreg operands to remove the subreg field. The code for this is in
>> VirtRegMap.cpp, around line 165. In short:
>>
>> PhysReg = MO.getReg();
>> if (MO.getSubReg() != 0) {
>> PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
>> MO.setSubReg(0);
>> }
>> MO.setReg(PhysReg);
>>
>> Adding this code to Gcra fixes the assembly issue for me. I've attached
>> my updated copy. Hope this helps.
>>
>>...
2016 Nov 27
5
Extending Register Rematerialization
...e rematerialized if the instruction
// doesn't read the other parts of the register. Otherwise it is really a
// read-modify-write operation on the full virtual register which cannot
be
// moved safely.
if (TargetRegisterInfo::isVirtualRegister(DefReg) &&
MI.getOperand(0).getSubReg() && MI.readsVirtualRegister(DefReg))
return false;
// Avoid instructions obviously unsafe for remat.
if (MI.isNotDuplicable() || MI.mayStore() || MI.hasUnmodeledSideEffects())
return false;
// Don't remat inline asm. We have no idea how expensive it is
// even if it...
2012 Nov 04
3
[LLVMdev] problem trying to write an LLVM register-allocation pass
My tst.bc is attached. I had to use ssh to copy it from my office
machine to my home laptop. In case that corrupts it, I also put a copy
here:
http://pages.cs.wisc.edu/~horwitz/LANG/tst.bc
I created the file like this:
clang -emit-llvm -O0 -c tst.c -o tst.bc
opt -mem2reg tst.bc > tst.mem2reg
mv tst.mem2reg tst.bc
Susan
On 11/4/2012 3:27 PM, Lang Hames wrote:
> Hi Susan,
>