search for: getstoresizeinbits

...InBits()/8 to compute IncrementSize, which is the offset for the load of second half of the vector. I have a situation where the frontend is producing load for a <2 x i1> type, and the architecture has i1 registers (but not v2i1 registers). The store size of i1 is 8 bits (the size returned by getStoreSizeInBits()). When SplitVecRes_LOAD is called, because it is using getSizeInBits()/8, the offset for the second half is zero, so it ends up using the same i1 value for both the halves. Is this a bug, or am I missing something? Thanks, Manjunath

...his failed assertion: llc: LegalizeDAG.cpp:1309: llvm::SDValue<unnamed>::SelectionDAGLegalize::LegalizeOp(llvm::SDValue): Assertion `0 && "This action is not supported yet!"' failed. I initially expected the if statement on line 1191 (in my copy), `if (SrcWidth != SrcVT.getStoreSizeInBits()` to catch my i16 promotion case - but it doesn't because SrcVT.getSizeInBits() and SrcVT.getStoreSizeInBits() equals 16 with SrcVT == MVT::i16. I'd appreciate any pointers in the right direction. Thank you, Alex