search for: getssaregmap

...MachineBasicBlock & mbb, unsigned src, unsigned dst ) { MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); const TargetRegisterClass *rc = mf.getSSARegMap()->getRegClass(dst); const MRegisterInfo * reg_info = mf.getTarget().getRegisterInfo(); reg_info->copyRegToReg(mbb, iter, dst, src, rc); } But the getRegClass method seems to expect a virtual register. Could someone fix this code for me? I could not find an example in the source of...

On Sun, 2 Jul 2006, Fernando Magno Quintao Pereira wrote: > MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); > const TargetRegisterClass *rc = mf.getSSARegMap()->getRegClass(dst); > const MRegisterInfo * reg_info = mf.getTarget().getRegisterInfo(); > reg_info->copyRegToReg(mbb, iter, dst, src, rc); > } > > But the getRegClass method seems to expect a virtual register. Could > someone fix this code for me? I could not find an...

Hello. I am making a backend for a virtual machine. But it does assume infinite number of virtual registers unlike those of usual machines. In this case, how can I implement this? Would you mind telling me some tips? Thank you so much. Seung Jae Lee

Given a live interval LI, what's the right way to get the register class of the interval? I'm assuming that all LiveRange entries in the LiveInterval are consistent in that if allocated to a register they would all go in the same register class. Fair assumption? If I take the first LiveRange LR from LI, look up its instruction/operand at "start" and then look at its

...k up its > instruction/operand at "start" and then look at its > TargetOperandInfo and send TOI::RegClass to > MRegisterInfo:getRegClass, is that sufficient. > > It seems way overly complicated. Umm...yeah. That way be dragons. :-/ Fortunately, I found MachineFunction::getSSARegMap()->getRegClass(LI.reg) which works swimmingly. -Dave

...). The virtual registers are defined by the range: [MRegisterInfo::FirstVirtualRegister, MRegisterInfo::FirstVirtualRegister+VirtRegInfo.size()] Alternatively, the same information can be obtained from the SSARegMap for the function: given a MachineFunction, use something like: NumVRegs = MF.getSSARegMap()->getLastVirtReg()+1; These also start from MRegisterInfo::FirstVirtualRegister. > But LiveIntervalAnalysis.h is not in > "include/llvm/CodeGen", so I have to either include it by: > > #include "../../llvm/lib/CodeGen/LiveIntervalAnalysis.h" > > or point...

One of my pass requires LiveIntervals to build the interference graph, because LiveVariables do not provide an interface to iterate through all viritual registers. But LiveIntervalAnalysis.h is not in "include/llvm/CodeGen", so I have to either include it by: #include "../../llvm/lib/CodeGen/LiveIntervalAnalysis.h" or point my project include path to

...ined by the range: > [MRegisterInfo::FirstVirtualRegister, > MRegisterInfo::FirstVirtualRegister+VirtRegInfo.size()] > > Alternatively, the same information can be obtained from the SSARegMap for > the function: given a MachineFunction, use something like: > > NumVRegs = MF.getSSARegMap()->getLastVirtReg()+1; > > These also start from MRegisterInfo::FirstVirtualRegister. I'm not sure if these two methods work because after the live intervals are joined, some virtual registers are coalesced, and their indices are invalidated. It's no longer that each register in:...

...<< Slot << "\n"); std::vector<LiveInterval*> Added = LIs->addIntervalsForSpills(*LI, *VRM, Slot); static unsigned J = 0; for (unsigned I = 0; I < Added.size(); ++I, ++J) { unsigned VReg = Added[I]->reg; const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VReg); TargetRegisterClass::const_iterator Iter = RC->allocation_order_begin(*MF); if (Iter + J >= RC->allocation_order_end(*MF)) J = 0; unsigned PReg = *(Iter + J); // **** Assign the newly-created live interval to a physical register VRM->assign...

> > Thank you Chris. I will try to implement the TwoAddress pass to run on > > machine code. Why it has not been originally implemented to run on > > machine code? > > I'm not sure what you mean. It definitely does run on machine code. I was thinking that it only transformed instructions with virtual registers because of this code in the TwoAddressInstructionPass.cpp:

On Mon, 26 Jun 2006, Fernando Magno Quintao Pereira wrote: >>> Thank you Chris. I will try to implement the TwoAddress pass to run on >>> machine code. Why it has not been originally implemented to run on >>> machine code? >> >> I'm not sure what you mean. It definitely does run on machine code. > > I was thinking that it only transformed

On Thu, 17 Aug 2006, Anton Vayvod wrote: > Thanks, Ralph, this line worked well :) > Here it is, my first patch to LLVM :) > I've changed all allocation_order_begin() and allocation_order_end() methods > to take const MachineFunction &MF as a parameter. I also added const version > of MachineFunction::getInfo<Ty>() method. And I changed three static hasFP() >

On Fri, 11 May 2007, David Greene wrote: > Umm...yeah. That way be dragons. :-/ > > Fortunately, I found > MachineFunction::getSSARegMap()->getRegClass(LI.reg) which > works swimmingly. Yep, that's exactly the right way to go for vregs. It won't work for physregs, primarily because they can be in multiple reg classes :) -Chris -- http://nondot.org/sabre/ http://llvm.org/

...; [MRegisterInfo::FirstVirtualRegister, >> MRegisterInfo::FirstVirtualRegister+VirtRegInfo.size()] >> >> Alternatively, the same information can be obtained from the SSARegMap for >> the function: given a MachineFunction, use something like: >> >> NumVRegs = MF.getSSARegMap()->getLastVirtReg()+1; >> >> These also start from MRegisterInfo::FirstVirtualRegister. > > I'm not sure if these two methods work because after the live > intervals are joined, some virtual registers are coalesced, and their > indices are invalidated. It's no lon...

...); > std::vector<LiveInterval*> Added = > LIs->addIntervalsForSpills(*LI, *VRM, Slot); > > static unsigned J = 0; > > for (unsigned I = 0; I < Added.size(); ++I, ++J) { > unsigned VReg = Added[I]->reg; > const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass > (VReg); > TargetRegisterClass::const_iterator Iter = > RC->allocation_order_begin(*MF); > if (Iter + J >= RC->allocation_order_end(*MF)) J = 0; > unsigned PReg = *(Iter + J); > > // **** Assign the newly-created live interval to a p...

> On Sun, 2 Jul 2006, Fernando Magno Quintao Pereira wrote: > > > MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); > > const TargetRegisterClass *rc = mf.getSSARegMap()->getRegClass(dst); > > const MRegisterInfo * reg_info = mf.getTarget().getRegisterInfo(); > > reg_info->copyRegToReg(mbb, iter, dst, src, rc); > > } > > > > But the getRegClass method seems to expect a virtual register. Could > > someone fix this co...