search for: getsextvalu

...eive TableGen error "Could not infer all types in, pattern!" (exact details written below). So far I'm not able to generate selection code with TableGen for the ADD_r* instructions, etc: def i64immSExt32 : PatLeaf<(imm), [{return isInt<32>(N->getSExtValue()); }]>; As in the case of https://groups.google.com/forum/#!topic/llvm-dev/LfltBGG9ru0 : "It seems that defining a new register class changes how the tblgen infers the types in the DAG patterns. So what is the right way to add a register class for a different type?" Ple...

...and are equal, the other indices >> // might be also be dynamically equal, so the GEPs can alias. >> if (C1 && C2 && C1 == C2) >> return MayAlias; > > Does changing this condition fix the issue? E.g > > if (C1 && C2 && C1->getSExtValue() == C2->getSExtValue()) { ... } Yes it does. Then it realize the two GEPs alias and I get the expected result. But since there is also a Value pointer comparison in bool BasicAAResult::isValueEqualInPotentialCycles(const Value *V, const Va...

I've been debugging some strange happenings over here and I put an assert in APInt to catch what I think is the source of the problem: int64_t getSExtValue() const { // An i1 -1 is unrepresentable. assert(BitWidth != 1 && "Signed i1 value is not representable!"); To me an i1 -1 makes no sense whatsoever. It is not representable in twos-complement form. It cannot be distinguished from unsigned i1 1. It turns out this asse...

Hi, It seems that opt thinks that the two pointers %_tmp2 = getelementptr [3 x i16], [3 x i16]* %a, i16 0, i64 1 and %_tmp4 = getelementptr [3 x i16], [3 x i16]* %a, i16 0, i16 1 does not alias? Is this intended or a bug? Details below: -------------- I found this when I ran opt on: define i16 @f () { %a = alloca [3 x i16] ; Write 98 at index 1 in the array. ; NB: using i64 as

Hi all, I have the condition of an ICmpInst in a variable called condition obtained doing GenericValue condition = getOperandValue(&I, SF); Now I would like to understand if the comparison was true or false. Is it correct to use condition.IntVal.getSExtValue() and if the value is 0 consider the true and if the value is -1 consider the condition false? I'm not sure because I was expecting something different and I'm a bit lost Should I use another approach? Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL...

Hi all, I want to match addition with 16bit integers. So I define a pattern fragment as follows: def simm16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; Now I am confused between (add R32:$dst, simm16:$im) and (add R32:$dst, (i32 simm16:$im)). Do both of them match the same pattern? Are they equivalent? If not what is the difference? I am also confused as to how ValueTypes relate to SDNodes as I think we are able to use both of them...

Hello. I've tried to add some simple arithmetic vector operations to the BPF backend available in the LLVM repo. Because I added in BPFRegisterInfo.td another RegisterClass (taken from the Mips backend): def MSA128W: RegisterClass<"BPF", [v2i64, v2f64], 128, (sequence "W%u", 0, 31)>; in order to support vector for example, ADD

...ideas what is the proper way to access the value '8' ? > > It's a ConstantInt, so cast it and retrieve the APInt then pull out the > number. Here: > > unsigned val; > if (ConstantInt *CI = dyn_cast<ConstantInt>(v)) { > val = CI->getValue()->getSExtValue(); > } > > Nick > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > -- View this message in context: http://www.nabble.co...

...l argument number. > Any other ideas what is the proper way to access the value '8' ? It's a ConstantInt, so cast it and retrieve the APInt then pull out the number. Here: unsigned val; if (ConstantInt *CI = dyn_cast<ConstantInt>(v)) { val = CI->getValue()->getSExtValue(); } Nick

I have an instruction: Instruction: %mask166 = and i128 %lvar_ins176, -18446462598732840961 I would like to get the value of the const above, I'm using getSExtValue; however, I obviously get an assert for "bit size" greater than 64 (since it's a i128 instruction). So how else can I get this value? Thanks. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/201...

Hi, I was wondering how I can print out the result of some arithmetic on 128 bit integers. After having a look at the API , it seems it is possible to get the integer value from the "ConstantInt::getSextValue() " but the return value is only a int64_t. I wish to print it on the console output and printing as a string or decimal ( using C standard library printf ) My Question : How can I get the returned value of a 128 bit ( or more number of bits ) arithmetic ? Thanks, Malhar --------...

...tic_cast<uint64_t>(-2), true); EXPECT_EQ(0u, i33minus2.countLeadingZeros()); EXPECT_EQ(32u, i33minus2.countLeadingOnes()); EXPECT_EQ(33u, i33minus2.getActiveBits()); EXPECT_EQ(1u, i33minus2.countTrailingZeros()); EXPECT_EQ(32u, i33minus2.countPopulation()); EXPECT_EQ(-2, i33minus2.getSExtValue()); EXPECT_EQ(((uint64_t)-2)&((1ull<<33) -1), i33minus2.getZExtValue()); } #endif Given that we are long past gcc 4.2, any chance someone with FreeBSD could check this now works and remove the XFAIL? Thanks very much Pete -------------- next part -------------- An HTML attachment wa...

...le. And the matcher table should call ISD::isBuildVectorAllOnes. I believe we use vnot with vXi1 vectors on X86 and I haven't seen any issues. The FIXME you pointed to seems related to a scalar patcher not a vector pattern. In that case the issue is that the immediate matcher for scalars calls getSExtValue on a 1-bit APInt which will return -1 in an int64_t. ~Craig On Wed, Feb 19, 2020 at 11:11 AM Tim Northover via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Hi Hendrik, > > On Wed, 19 Feb 2020 at 11:01, Hendrik Greving via llvm-dev > <llvm-dev at lists.llvm.org> wrote...

I am processing the LLVM instructions and right now I am at the 'call' instruction. For now I just want to print the argument type. For example in the following: %0 = tail call i32 (...)* @__FFF (i32 8) nounwind; <i32> [#uses=1] I need to get access to 'i32' and '8' separately. I do: CallInst *CI = dyn_cast<CallInst>(I); Value *v = CI->getOperand(1)

So the problem here was trying to return MIN_VALUE zero extended, if I return sign extended than this issue is resolved; however, I still get an error with getSExtValue when trying to get the value of the const from Instruction: %mask166 = and i128 %lvar_ins176, -18446462598732840961 On Fri, Nov 16, 2012 at 3:17 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > Eli, > > Thanks for responding. Yes, I read the error message but it seems odd > t...

...to access the value '8' ? >> >> It's a ConstantInt, so cast it and retrieve the APInt then pull out the >> number. Here: >> >> unsigned val; >> if (ConstantInt *CI = dyn_cast<ConstantInt>(v)) { >> val = CI->getValue()->getSExtValue(); >> } >> >> Nick >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >> >> > > -- Vi...

The code below is triggering some weird behavior that's different from how gcc treats this inline asm. Clang keeps the original type of "loc" as "bool", which generates an "i1 true" after inlining. So far so good. However, during ISEL, the "true" is converted to a signed integer. So when it's evaluated, the result is this: .quad

...sBuildVectorAllOnes. I believe we use vnot with vXi1 vectors on >> X86 and I haven't seen any issues. >> >> The FIXME you pointed to seems related to a scalar patcher not a vector >> pattern. In that case the issue is that the immediate matcher for scalars >> calls getSExtValue on a 1-bit APInt which will return -1 in an int64_t. >> >> ~Craig >> >> >> On Wed, Feb 19, 2020 at 11:11 AM Tim Northover via llvm-dev < >> llvm-dev at lists.llvm.org> wrote: >> >>> Hi Hendrik, >>> >>> On Wed, 19 Feb 2020 a...

Eli, Thanks for responding. Yes, I read the error message but it seems odd that it would be trying to use more than 64 bits. It compiles and executes in gcc on 32 bit arch just fine. I'll probably take your suggestion and file a bug with a reduced testcase. Thanks again, Ryan On Fri, Nov 16, 2012 at 3:10 PM, Eli Friedman <eli.friedman at gmail.com>wrote: > On Fri, Nov 16, 2012

...diate node and get the lower 16 bits. // Transformation Function - get the higher 16 bits. def HI16 : SDNodeXForm<imm, [{ return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); }]>; Similarly, get the high 16 bits. def LUiORiPred : PatLeaf<(imm), [{ int64_t SVal = N->getSExtValue(); return isInt<32>(SVal) && (SVal & 0xffff); }]>; For completeness sake I've included this, but it's return true there are bits in both 16 bit fragments. Then we use (here VT = i32, ORiOp is our logical or which takes an immediate, LUiOp loads the upper bits of a...