search for: getsetccinverse

...E: case ISD::SETNE: CondCode = XXXCC::COND_NE; break; case ISD::SETUO: CondCode = XXXCC::COND_UN; break; case ISD::SETO: case ISD::SETUEQ: case ISD::SETUGT: case ISD::SETUGE: case ISD::SETULT: case ISD::SETULE: case ISD::SETUNE: CC = getSetCCInverse(CC,false); getFPCCtoMBCC(CC,CondCode); break; } } I am generating wrong code when using floating point library call for comparions. For the following simple case: float branchTest(float a, float b) { float retVal; if (a == b) { retVal = a / b + 22.34; } return retVal; } I am getting...

...; break; > case ISD::SETUO: > CondCode = XXXCC::COND_UN; > break; > case ISD::SETO: > case ISD::SETUEQ: > case ISD::SETUGT: > case ISD::SETUGE: > case ISD::SETULT: > case ISD::SETULE: > case ISD::SETUNE: > CC = getSetCCInverse(CC,false); > getFPCCtoMBCC(CC,CondCode); > break; > } > } > > I am generating wrong code when using floating point library call for > comparions. For the following simple case: > float branchTest(float a, float b) { > float retVal; > if (a == b) { > r...

...>> case ISD::SETO: >> case ISD::SETUEQ: >> case ISD::SETUGT: >> case ISD::SETUGE: >> case ISD::SETULT: >> case ISD::SETULE: >> case ISD::SETUNE: >> CC = getSetCCInverse(CC,false); >> getFPCCtoMBCC(CC,CondCode); >> break; >> } >> } >> >> I am generating wrong code when using floating point library >> call for >> comparions. For the following simple...

Hi All, I noticed LLVM target independent side is converting an ordered less than "setolt" into unordered greater than "setuge" operation. There are no target hooks to control going from the ordered mode into unordered. I am trying to figure out the best way to support unordered operation on Hexagon. We don't have a single instruction to do unordered operation. So we

...s. I would prefer target independent part not to transform > ordered ops into unordered. Is it a good idea? How do other targets > support this feature? > > I don't have a lot of experience dealing with floating points. I will > really appreciate any help here. The function ISD::getSetCCInverse() would probably be useful for you here: you can use it to transform an unordered operation into an ordered operation. -Eli

> The function ISD::getSetCCInverse() would probably be useful for you > here: you can use it to transform an unordered operation into an > ordered operation. Thanks for your reply Eli. I will check how to convert unordered operations back to ordered one. I have another related question - is it possible for frontend (clang) to...

...bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); if (TrueWhenTrue) return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); // Invert the condition. ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); CC = ISD::getSetCCInverse(CC, N0.getOperand(0).getValueType().isInteger()); return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); } and the AND is then dropped by TargetLowering::SimplifyDemandedBits ... switch (Op.getOpcode()) { ... case ISD::AND: // If the RHS is a consta...

...ISD::SETEQ) ^ > (N1C->getAPIntValue() != 1); > if (TrueWhenTrue) > return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); > > // Invert the condition. > ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); > CC = ISD::getSetCCInverse(CC, > > N0.getOperand(0).getValueType().isInteger()); > return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), > CC); > } > > > and the AND is then dropped by > > TargetLowering::SimplifyDemandedBits > > ... > > > switch...

On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote: > Bill Wendling wrote: >> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: >> >>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >>> >>>> Our architecture has 1-bit boolean predicate registers. >>>> >>>> I've defined comparison >>>> >>>> def

Bill Wendling wrote: > On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: > >> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >> >>> Our architecture has 1-bit boolean predicate registers. >>> >>> I've defined comparison >>> >>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set