search for: getsetcc

We have is a problem in getSetCCResult(), which we overload because we support setCC for vectors. However, where other targets can get away with merely converting the EVT that gets passed to getSetCCResult() to an integer type (which EVT conveniently provides a method to do), we need to convert to int AND promote to i32 (or, in so...

Hi, The attached patch implements sub.ovf/mul.ovf intrinsics similarly to the recently added add.ovf intrinsics. These are useful for implementing some vm instructions like sub.ovf/mul.ovf in .NET IL efficiently. sub.ovf is supported in target independent lowering and on x86, while mul.ovf is only supported in the x86 backend. Please review

...perand RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(1), DAG.getConstant(1, MVT::i32)); // Expand SDOperand Lo = DAG.getNode(N->getOpcode(), MVT::i32, LHSL, RHSL); ISD::CondCode CarryCC = (N->getOpcode() == ISD::ADD) ? ISD::SETULT : ISD::SETUGT; SDOperand Carry = DAG.getSetCC(MVT::i32, Lo, LHSL, CarryCC); SDOperand Hi = DAG.getNode(N->getOpcode(), MVT::i32, LHSH, Carry); Hi = DAG.getNode(N->getOpcode(), MVT::i32, Hi, RHSH); // Merge the pieces return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).Val; } In LowerOperation I lower add and sub using: case ISD::ADD...

I'm running into lots of problems with this call back. Mostly the problem occurs because this callback is used before types are legalized. However, the code generator does not have a 1-1 correspondence between all LLVM types and the codegen types. This leads to problems when getSetCCResultType is passed in an invalid type, but has a valid LLVM type attached to it. An example is <3 x float>. getSetCCResultType can return any type, and in the AMDIL backends case, for a <3 x float>, returns the corresponding integer version of the vector. The problem comes in code like...

My target doesn't support 64 bit arithmetic, so I'd like to supply definitions for adde/addc. The problem is I can't seem to figure out the magic. Here's an example of what I need to generate: # two i64s in r5/r6 and r7/r8 # result in r1/r2, carry in r3 # adde add r2, r6, r8 cmpltu r3, r2, r6 # compute carry # addc add r1, r5, r7 add r1, zero, r3 Is this

Hi Micah, I think that getSetCCResultType should only be called for legal types. Disabling it on isPow2VectorType is not the way to go because there are other illegal vector types which are pow-of-two. I suggest that you call it only after type-legalization. BTW, you can't set the LLVMTy yourself because you don't have ac...

...torType()))) But the comment right after it is: // sext(setcc) -> sext_in_reg(vsetcc) for vectors. // Only do this before legalize for now. if (VT.isVector() && !LegalOperations) { So, these optimizations are never safe in the general case if we can't guarantee that TLI.getSetCCResultType() returns a valid type. From: Rotem, Nadav [mailto:nadav.rotem at intel.com] Sent: Friday, July 27, 2012 12:25 PM To: Villmow, Micah; Developers Mailing List Subject: RE: TLI.getSetCCResultType() and/or MVT broken by design? Hi Micah, I think that getSetCCResultType should only be call...

...wo does not guarantee anything about its legality. For example <128 x i64> would pass the condition in the code below, and die on most targets. From: Villmow, Micah [mailto:Micah.Villmow at amd.com] Sent: Friday, July 27, 2012 22:33 To: Rotem, Nadav; Developers Mailing List Subject: RE: TLI.getSetCCResultType() and/or MVT broken by design? if (N0.getOpcode() == ISD::SETCC && (LegalOperations || (!LegalOperations && VT.isPow2VectorType()))) But the comment right after it is: // sext(setcc) -> sext_in_reg(vsetcc) for vectors. // Only do this before lega...

...> > I did a quick study of these funnel shifts: > The generic lowering to SDAG is correct for the optimization below. It > actually stops poison if shift amount is zero: > SDValue ShAmt = DAG.getNode(ISD::UREM, sdl, VT, Z, BitWidthC); > (...) > SDValue IsZeroShift = DAG.getSetCC(sdl, CCVT, ShAmt, Zero, ISD::SETEQ); > setValue(&I, DAG.getSelect(sdl, VT, IsZeroShift, IsFSHL ? X : Y, Or)); > > This is assuming select in SDAG stops poison in the same way we've > proposed > for the IR. > > However, the lowering has 2 optimizations. It can lower...

...bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); if (TrueWhenTrue) return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); // Invert the condition. ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); CC = ISD::getSetCCInverse(CC, N0.getOperand(0).getValueType().isInteger()); return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); } and the AND is then dropped by TargetLowering::SimplifyDemandedBits ... switch (Op.getOpcode()) { ... case ISD::AND: // If the RHS is a...

...TheXor = Op0.getNode(); >> Equal = true; >> } >> >> SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1; >> >> EVT SetCCVT = NodeToReplace.getValueType(); >> if (LegalTypes) >> SetCCVT = TLI.getSetCCResultType(SetCCVT); >> SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), >> SetCCVT, >> Op0, Op1, >> Equal ? ISD::SETEQ : ISD::SETNE); >> // R...

...> > I did a quick study of these funnel shifts: > The generic lowering to SDAG is correct for the optimization below. It > actually stops poison if shift amount is zero: > SDValue ShAmt = DAG.getNode(ISD::UREM, sdl, VT, Z, BitWidthC); > (...) > SDValue IsZeroShift = DAG.getSetCC(sdl, CCVT, ShAmt, Zero, ISD::SETEQ); > setValue(&I, DAG.getSelect(sdl, VT, IsZeroShift, IsFSHL ? X : Y, Or)); > > This is assuming select in SDAG stops poison in the same way we've proposed > for the IR. > > However, the lowering has 2 optimizations. It can lower funne...

...hasOneUse() && Op0.getOpcode() == ISD::XOR) { TheXor = Op0.getNode(); Equal = true; } SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1; EVT SetCCVT = NodeToReplace.getValueType(); if (LegalTypes) SetCCVT = TLI.getSetCCResultType(SetCCVT); SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), SetCCVT, Op0, Op1, Equal ? ISD::SETEQ : ISD::SETNE); // Replace the uses of XOR with SETCC Work...

...0.getOpcode() == ISD::XOR) { > TheXor = Op0.getNode(); > Equal = true; > } > > SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1; > > EVT SetCCVT = NodeToReplace.getValueType(); > if (LegalTypes) > SetCCVT = TLI.getSetCCResultType(SetCCVT); > SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), > SetCCVT, > Op0, Op1, > Equal ? ISD::SETEQ : ISD::SETNE); > // Replace the uses of XOR wi...

There's a question about the behavior of funnel shift [1] + select and poison here that reminds me of previous discussions about select and poison [2]: https://github.com/AliveToolkit/alive2/pull/32#discussion_r257528880 Example: define i8 @fshl_zero_shift_guard(i8 %x, i8 %y, i8 %sh) { %c = icmp eq i8 %sh, 0 %f = fshl i8 %x, i8 %y, i8 %sh %s = select i1 %c, i8 %x, i8 %f ; shift amount is 0

...DebugLoc dl = N->getDebugLoc(); // Get the incoming operand to be shifted. SDValue InL, InH; GetExpandedInteger(N->getOperand(0), InL, InH); SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy); SDValue Amt2 = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt); SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy), Amt, NVBitsNode, ISD::SETULT); SDValue Lo1, Hi1, Lo2, Hi2; switch (N->getOpcode()) { default: llvm_unreachable("Unknown shift"); case ISD::SHL: // ShAmt < NVTBits Lo1 = DAG.getConstant(0, NVT);...

...ISD::SETEQ) ^ > (N1C->getAPIntValue() != 1); > if (TrueWhenTrue) > return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); > > // Invert the condition. > ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); > CC = ISD::getSetCCInverse(CC, > > N0.getOperand(0).getValueType().isInteger()); > return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), > CC); > } > > > and the AND is then dropped by > > TargetLowering::SimplifyDemandedBits > > ... > > >...

...ueType(0); APFloat apf(DAG.EVTToAPFloatSemantics(VT), APInt::getNullValue(VT.getSizeInBits())); APInt x = APInt::getSignBit(NVT.getSizeInBits()); (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); Tmp1 = DAG.getConstantFP(apf, dl, VT); Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT), Node->getOperand(0), Tmp1, ISD::SETLT); True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); // TODO: Should any fast-math-flags be set for the FSUB? False = DAG.getNode(ISD::FP_TO_SINT, dl,...

...: > > The generic lowering to SDAG is correct for the optimization below. > It > > actually stops poison if shift amount is zero: > > SDValue ShAmt = DAG.getNode(ISD::UREM, sdl, VT, Z, BitWidthC); > > (...) > > SDValue IsZeroShift = DAG.getSetCC(sdl, CCVT, ShAmt, Zero, > > ISD::SETEQ); > > setValue(&I, DAG.getSelect(sdl, VT, IsZeroShift, IsFSHL ? X : > > Y, Or)); > > > > This is assuming select in SDAG stops poison in the same way we've > > proposed > > for the...

...s(VT), > > APInt::getNullValue(VT.getSizeInBits())); > > APInt x = APInt::getSignMask(NVT.getSizeInBits()); > > (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); > > Tmp1 = DAG.getConstantFP(apf, dl, VT); > > Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT), > > Node->getOperand(0), > > Tmp1, ISD::SETLT); > > True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); > > // TODO: Should any fast-math-flags be set for the FSUB? >...