Displaying 2 results from an estimated 2 matches for "getschedwrit".
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getschedwrite
2014 Feb 18
2
[LLVMdev] Question about per-operand machine model
Hi Andy and all,
I have a question about per-operand machine model. I am finding some
relations between 'MCWriteLatencyEntry' and 'MCWriteProcResEntry'.
For example,
class InstTEST<..., InstrItinClass itin> : Instruction {
let Itinerary = Itin;
}
// I assume this MI writes 2 registers.
def TESTINST : InstTEST<..., II_TEST>
// schedule info
II_TEST:
2014 Feb 18
2
[LLVMdev] Question about per-operand machine model
...======================================================
--- utils/TableGen/SubtargetEmitter.cpp (revision 201607)
+++ utils/TableGen/SubtargetEmitter.cpp (working copy)
@@ -932,12 +932,7 @@
WLEntry.Cycles = 0;
unsigned WriteID = WriteSeq.back();
WriterNames.push_back(SchedModels.getSchedWrite(WriteID).Name);
- // If this Write is not referenced by a ReadAdvance, don't distinguish it
- // from other WriteLatency entries.
- if (!SchedModels.hasReadOfWrite(
- SchedModels.getSchedWrite(WriteID).TheDef)) {
- WriteID = 0;
- }
+
WLEntry.WriteRe...