Displaying 6 results from an estimated 6 matches for "getschedclass".
2011 Nov 29
0
[LLVMdev] Querying instruction classes
Hello,
I believe MCInstrDesc::getSchedClass() is what you're looking for.
-Jim
On Nov 28, 2011, at 5:03 PM, Evandro Menezes wrote:
> I'd appreciate some help in figuring out how to determine which
> InstrItinClass an instruction belongs to.
>
> For example, an InstrItinClass is defined in Schedule.td as:
>
> d...
2015 Jan 08
4
[LLVMdev] Machine LICM and cheap instructions?
...ItinData,
const MachineInstr *DefMI, unsigned DefIdx) const {
if (!ItinData || ItinData->isEmpty())
return false;
unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
if (DDomain == ARMII::DomainGeneral) {
unsigned DefClass = DefMI->getDesc().getSchedClass();
int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
return (DefCycle != -1 && DefCycle <= 2);
}
return false;
}
So it won't hoist instructions that have defined operands ready in at most two cycles for general-domain instructions. Regardless, I don't un...
2011 Nov 29
2
[LLVMdev] Querying instruction classes
I'd appreciate some help in figuring out how to determine which
InstrItinClass an instruction belongs to.
For example, an InstrItinClass is defined in Schedule.td as:
def FOO : InstrItinClass;
Which is then used to build an InstrItinData in ProcessorItineraries and
to specify the class of a particular instruction.
I'd like to find out from a given instruction which class it belongs
2016 Jan 06
2
DFAPacketizer, Scheduling and LoadLatency
On Tue, Nov 17, 2015 at 11:15 AM, Krzysztof Parzyszek <
kparzysz at codeaurora.org> wrote:
> On 11/17/2015 12:26 PM, Rail Shafigulin wrote:
>
>>
>> I tried setting
>> let mayLoad = 1 {
>> class InstrLD .... {
>> }
>> }
>>
>> But that didn't seem to work. When I looked at the debug output the
>> latency for the load
2015 Nov 16
2
DFAPacketizer assert failure
...assert(CachedTable.count(StateTrans) != 0);
in the following function:
// reserveResources - Reserve the resources occupied by a MCInstrDesc and
// change the current state to reflect that change.
void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) {
unsigned InsnClass = MID->getSchedClass();
const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
unsigned FuncUnits = IS->getUnits();
UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits);
ReadTable(CurrentState);
assert(CachedTable.count(StateTrans) != 0);
CurrentState = CachedTable[StateTrans];
}
This...
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...gt; + if (MI->isInlineAsm())
>> + return false;
>> +
>> + // We check if MI has any functional units mapped to it.
>> + // If it doesn't, we ignore the instruction.
>> + const MCInstrDesc& TID = MI->getDesc();
>> + unsigned SchedClass = TID.getSchedClass();
>> + const InstrStage* IS = ResourceTracker->getInstrItins()->beginStage(SchedClass);
>> + unsigned FuncUnits = IS->getUnits();
>> + return !FuncUnits;
>> +}
>> +
>> +// isSoloInstruction: - Returns true for instructions that must be
>> +// s...