Displaying 14 results from an estimated 14 matches for "getresno".
2009 Nov 13
3
[LLVMdev] legalize dag problem
...Tmp3 = LegalizeOp(Tmp1);
Tmp4 = LegalizeOp(Tmp1.getValue(1)); <----------------- what
is the value expected
}
What is the value supposed to legalized by the second call to legalizeOp. ?
My problem is that the second call asserts inside legalize ops at
ResultVals[Op.getResNo()]; b'cos ResultVals has only 1 element and
Op.resno is 0.
I am not sure if I provided enough context. Please let me know if more
information is needed.
thanks
shrey
2018 May 30
2
InstrEmitter::CreateVirtualRegisters handling of CopyToReg
...Registers(SDNode
*Node,
if (!VRBase && !IsClone && !IsCloned)
for (SDNode *User : Node->uses()) {
if (User->getOpcode() == ISD::CopyToReg &&
User->getOperand(2).getNode() == Node &&
User->getOperand(2).getResNo() == i) {
unsigned Reg =
cast<RegisterSDNode>(User->getOperand(1))->getReg();
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
- const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
- if (RegRC == RC) {
+ // Allow constr...
2009 Nov 13
0
[LLVMdev] legalize dag problem
> My problem is that the second call asserts inside legalize ops at
> ResultVals[Op.getResNo()]; b'cos ResultVals has only 1 element and
> Op.resno is 0.
Looks like you lowered the load improperly. It should return 2 values:
the value loaded and a chain.
--
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University
2009 Nov 13
1
[LLVMdev] legalize dag problem
...rand(1),
load->getBasePtr(), des };
DAG.getNode(CustomOpc, NodeTys, Ops, 4);
thanks again!
shrey
On Thu, Nov 12, 2009 at 4:41 PM, Anton Korobeynikov
<anton at korobeynikov.info> wrote:
>> My problem is that the second call asserts inside legalize ops at
>> ResultVals[Op.getResNo()]; b'cos ResultVals has only 1 element and
>> Op.resno is 0.
> Looks like you lowered the load improperly. It should return 2 values:
> the value loaded and a chain.
>
> --
> With best regards, Anton Korobeynikov
> Faculty of Mathematics and Mechanics, Saint Petersburg...
2017 Sep 27
0
Custom lower multiple return values
...may
be dropping the carry bit based on the semantics observed above, but don’t
know AArch64 well enough to verify.
SDValue MyTarget::LowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const {
EVT VT = Op.getValueType();
SDLoc dl(Op);
unsigned Opc = Op.getOpcode();
unsigned ResNo = Op.getResNo();
assert(Opc == ISD::UMUL_LOHI || Opc == ISD::SMUL_LOHI);
assert(ResNo == 0 || ResNo == 1);
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
unsigned MULHXOpcode = Opc == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS;
SDValue res[2] = { // Seems wasteful to genera...
2019 Jul 03
3
optimisation issue in an llvm IR pass
Hi Craig,
On 03.07.19 17:33, Craig Topper wrote:
> Don't the CreateICmp calls return a Value* with an i1 type? But then
> they are added to an i8 type? Not sure that works.
I had that initially:
auto cf = IRB.CreateICmpULT(Incr, ConstantInt::get(Int8Ty, 1));
auto carry = IRB.CreateZExt(cf, Int8Ty);
Incr = IRB.CreateAdd(Incr, carry);
it makes no difference to the generated assembly
2015 Aug 17
4
Aggregate load/stores
...th
7.28% lacsap lacsap [.]
llvm::SDNode::use_iterator::operator++
5.59% lacsap lacsap [.]
llvm::SDNode::use_iterator::operator!=
4.65% lacsap lacsap [.] llvm::SDNode::hasNUsesOfValue
3.82% lacsap lacsap [.] llvm::SDUse::getResNo
2.33% lacsap lacsap [.] llvm::SDValue::getResNo
2.19% lacsap lacsap [.] llvm::SDUse::getNext
1.32% lacsap lacsap [.]
llvm::SDNode::use_iterator::getUse
1.28% lacsap lacsap [.] llvm::SDUse::getUser
Here's the LLVM I...
2017 Jan 23
2
returning from LowerOperation()
> On Jan 23, 2017, at 12:36, Friedman, Eli via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>
> On 1/23/2017 5:21 AM, Jonas Paulsson wrote:
>> Hi Eli,
>>
>> I would like to clarify generally what the difference is between returning SDValue() and Op (input argument unchanged) from LowerOperation()?
>>
>> My understanding is that returning SDValue()
2009 Feb 11
0
[LLVMdev] Bug in SelectionDAGBuild.cpp?
...MVT MinVT = TLI.getRegisterType(MVT::i32);
if (VT.bitsLT(MinVT))
VT = MinVT;
}
This is occurring when VT is a 16bit vector type,<2x i8>. LLVM is then
changing it to be a 32bit type and
it asserts in :
getCopyToParts(DAG, SDValue(RetOp.getNode(), RetOp.getResNo() + j),
&Parts[0], NumParts, PartVT, ExtendKind);
Here:
assert(ValueVT.getVectorElementType() == PartVT &&
ValueVT.getVectorNumElements() == 1 &&
"Only trivial vector-to-scalar conversions should get
here!");...
2010 Feb 26
2
[LLVMdev] Possible SelectionDAG Bug
...oSelectionDAG::ReplaceAllUsesOfValuesWith:
// Read up all the uses and make records of them. This helps
// processing new uses that are introduced during the
// replacement process.
SmallVector<UseMemo, 4> Uses;
for (unsigned i = 0; i != Num; ++i) {
unsigned FromResNo = From[i].getResNo();
SDNode *FromNode = From[i].getNode();
#ifndef NDEBUG
assert(FromNode->getOpcode() != ISD::DELETED_NODE && "FromNode deleted!");
#endif
This triggers all over the place in the testbase. Is it expected that we
could get a deleted node here? The following code appe...
2015 Aug 17
5
Aggregate load/stores
I've definitely "run into this problem", and I would very much love to
remove my kludges [that are incomplete, because I keep finding places where
I need to modify the code-gen to "fix" the same problem - this is probably
par for the course from a complete amateur compiler writer and someone that
has only spent the last 14 months working (as a hobby) with LLVM].
So whilst
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
..., dl, MVT::Other,
- Tmp1, Lo, Tmp3, Hi, Tmp3);
- else
- Result = DAG.getNode(ISD::RET, dl, MVT::Other, Tmp1, Lo, Tmp3);
- Result = LegalizeOp(Result);
- } else {
- SDNode *InVal = Tmp2.getNode();
- int InIx = Tmp2.getResNo();
- unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
- MVT EVT = InVal->getValueType(InIx).getVectorElementType();
-
- // Figure out if there is a simple type corresponding to this Vector
- // type. If so, convert to the vector type....