search for: getrepregclassfor

...gisterClass<"TriCore", [i64], 32, > (add E0, E2, E4, E6, E8, E10, E12, E14)> { > let SubRegClasses = [(DR sub_even, sub_odd)]; > } > > And the DX and EX registers are defined this way: The regclasses look fine... So, you need to figure out why getRepRegClassFor() returns NULL in this case. Side note: you can autogenerate register names :) -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University

...uot;, [i64], 32, >> (add E0, E2, E4, E6, E8, E10, E12, E14)> { >> let SubRegClasses = [(DR sub_even, sub_odd)]; >> } >> >> And the DX and EX registers are defined this way: > The regclasses look fine... So, you need to figure out why > getRepRegClassFor() returns NULL in this case. Well, that's rather easy :-) The register class is not registered in the constructor of TriCoreTargetLowering. Maybe, some background is missing here: - I added the ER register class for MVT::i64 and I had to take care of quite a lot of stuff as the TriCore does n...

...(add E0, E2, E4, E6, E8, E10, E12, E14)> { >>> let SubRegClasses = [(DR sub_even, sub_odd)]; >>> } >>> >>> And the DX and EX registers are defined this way: >> The regclasses look fine... So, you need to figure out why >> getRepRegClassFor() returns NULL in this case. > Well, that's rather easy :-) The register class is not registered in > the constructor of TriCoreTargetLowering. Maybe, some background is > missing here: > > - I added the ER register class for MVT::i64 and I had to take care of > quite a lot of...

...b) nounwind readnone { entry: %div = sdiv i32 %a, %b ; <i32> [#uses=1] ret i32 %div } 4. Instruction Scheduling calls GetCostForDef (in ScheduleDAGRRList.cpp) when hitting the EXTRACT_SUBREG-Node introduced by the Pattern above. 5. GetCostForDef crashes here, as getRepRegClassFor(VT /* == MVT::i64 */) returns NULL: RegClass = TLI->getRepRegClassFor(VT)->getID(); For LLVM versions before 3.1 this did not happen (I don't know why). Solving this problem at the tablegen level means (I guess) not to use an explicitly modelled "ER" register class at all, rig...

...le/parameter is assigned something else than an MVT. Are there any general objections to replace EVT with MVT in these cases? For example, a quick look at TargetLowering.h give me this list of (member) functions, taking an EVT parameter, that asserts if the argument is not an MVT: getRegClassFor, getRepRegClassFor, getRepRegClassCostFor, setTypeAction, getLoadExtAction, isLoadExtLegal, getTruncStoreAction, isTruncStoreLegal, getIndexedLoadAction, getIndexedStoreAction, getCondCodeAction, getTypeToPromoteTo, addRegisterClass Regards, Patrik Hägglund -------------- next part -------------- An HTML attachment...

...| 2 +- lib/Target/Mips/MipsISelLowering.cpp | 6 +- 13 files changed, 87 insertions(+), 78 deletions(-) commit 9add28389f360a0aa3f21b282a025c957309093f Author: Patrik Hägglund <patrik.h.hagglund at ericsson.com> Date: Tue Dec 4 10:59:05 2012 +0100 Change TargetLowering::getRepRegClassFor to take an MVT, instead of EVT. Accordingly, change RegDefIter to contain MVTs instead of EVTs. include/llvm/Target/TargetLowering.h | 5 ++--- lib/CodeGen/MachineLICM.cpp | 2 +- lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 16 ++++++++-------- lib/CodeGen/...

...sdiv i32 %a, %b ; <i32> [#uses=1] > ret i32 %div > } > > 4. Instruction Scheduling calls GetCostForDef (in > ScheduleDAGRRList.cpp) when hitting the EXTRACT_SUBREG-Node introduced > by the Pattern above. > > 5. GetCostForDef crashes here, as getRepRegClassFor(VT /* == MVT::i64 > */) returns NULL: > > RegClass = TLI->getRepRegClassFor(VT)->getID(); This isn't really my area of expertise, but I think you're messing up your RegisterClass definition. Look at how ARM defines DTriple. -Eli

On Mon, Aug 20, 2012 at 12:01 AM, Fabian Scheler <fabian.scheler at gmail.com> wrote: > Hi Eli, > >>>>> 2. Storing arbitrary sized integers >>>>> >>>>> The testcase "test/CodeGen/Generic/APIntLoadStore.ll" checks for >>>>> loading/storing e.g. i33 integers from/into global variable. The >>>>> questions

Hi, Yes, that's what I would do. If you want LLVM and the register allocator to also know that the instruction explicitly defines the register, I would designate the register into it's own register class and have your instruction write to that class (and there will be only a single option for RA). cheers, Sam Sam Parker Research Student Electronic Systems Design Group Loughborough

...> > I had to chain mine nodes, because otherwise nodes xmac and srxacc got > removed on first combine. But since they are chained, they have > MVT::Other return type, and that causes strange crash inside func > GetCostFor in ScheduleDAGRRList.cpp: > > Def RegClass = TLI->getRepRegClassFor(VT)->getID(); > When VT is MVT::Other it returns 0x0, what results crash. > > It got me confused, because reading documentation on CodeGen gave me > an idea, that chain edges are control flow edges, not data edges. So I > don't understand why scheduler tries to assign some r...

> This isn't really my area of expertise, but I think you're messing up > your RegisterClass definition. Look at how ARM defines DTriple. DTriple is untyped :) , because we do not have any valut type which defines 3xi64. However, the paired register needs to have type. Fabian, what are the definitions of ER and DR register classes? -- With best regards, Anton Korobeynikov Faculty

2012/8/21 Anton Korobeynikov <anton at korobeynikov.info>: >> This isn't really my area of expertise, but I think you're messing up >> your RegisterClass definition. Look at how ARM defines DTriple. > DTriple is untyped :) , because we do not have any valut type which > defines 3xi64. > However, the paired register needs to have type. > > Fabian, what are

...ed something else than an MVT. Are there any general objections to replace EVT with MVT in these cases? > > For example, a quick look at TargetLowering.h give me this list of (member) functions, taking an EVT parameter, that asserts if the argument is not an MVT: > > getRegClassFor, getRepRegClassFor, getRepRegClassCostFor, setTypeAction, getLoadExtAction, isLoadExtLegal, getTruncStoreAction, isTruncStoreLegal, getIndexedLoadAction, getIndexedStoreAction, getCondCodeAction, getTypeToPromoteTo, addRegisterClass > Please do. MVT is cheaper than EVT and conceptually cleaner when dealing wit...

...E4, E6, E8, E10, E12, E14)> { >>>> let SubRegClasses = [(DR sub_even, sub_odd)]; >>>> } >>>> >>>> And the DX and EX registers are defined this way: >>> >>> The regclasses look fine... So, you need to figure out why >>> getRepRegClassFor() returns NULL in this case. >> >> Well, that's rather easy :-) The register class is not registered in >> the constructor of TriCoreTargetLowering. Maybe, some background is >> missing here: >> >> - I added the ER register class for MVT::i64 and I had to tak...

...E10, E12, E14)> { >>>>> let SubRegClasses = [(DR sub_even, sub_odd)]; >>>>> } >>>>> >>>>> And the DX and EX registers are defined this way: >>>> The regclasses look fine... So, you need to figure out why >>>> getRepRegClassFor() returns NULL in this case. >>> Well, that's rather easy :-) The register class is not registered in >>> the constructor of TriCoreTargetLowering. Maybe, some background is >>> missing here: >>> >>> - I added the ER register class for MVT::i64 and I...

Hi Eli, >>>> 2. Storing arbitrary sized integers >>>> >>>> The testcase "test/CodeGen/Generic/APIntLoadStore.ll" checks for >>>> loading/storing e.g. i33 integers from/into global variable. The >>>> questions are the same as regarding feature 1: How important is this >>>> feature? Is it save to ignore it? Is there