search for: getregistername

...3 = MI->getOperand(3); - O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); + O << '\t' << "mov"; printSBitModifierOperand(MI, 6, O); printPredicateOperand(MI, 4, O); O << '\t' << getRegisterName(Dst.getReg()) - << ", " << getRegisterName(MO1.getReg()); + << ", " << getRegisterName(MO1.getReg()) + << ", " << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));; if (ARM_AM::getSORegShOp(MO3.getImm(...

On Jun 22, 2011, at 9:00 AM, Renato Golin wrote: > On 22 June 2011 16:50, Jim Grosbach <grosbach at apple.com> wrote: >>> This sounds like a dead end as newer binutils are GPLv3. >> >> Yeah, that's definitely a very real concern and a big motivation to get the MC based asm parser whipped into usable shape. We're much more in control of our own destiny then.

On Oct 28, 2013, at 2:02 PM, Tyler Hardin <tghardin1 at catamount.wcu.edu> wrote: > See the source here: https://github.com/earl/llvm-mirror/blob/master/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp. It looks like getRegisterName might do what you want, but I don't know where it's coming from. (Whether it's a function or a member of a super class. Hopefully, if it's a member, it's public.) Looks like X86ATTInstPrinter::getRegisterName() and X86IntelInstPrinter::getRegisterName() are static, public membe...

See the source here: https://github.com/earl/llvm-mirror/blob/master/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp. It looks like getRegisterName might do what you want, but I don't know where it's coming from. (Whether it's a function or a member of a super class. Hopefully, if it's a member, it's public.) PS Sorry for the duplicate, Stephen. I forgot to CC the list. On Oct 28, 2013 12:03 PM, "Stephen Checkoway&quo...

I'm iterating over MCInsts and I'd like to examine particular instructions. For example, I'd like to look at all x86 CALL64m instructions. I may be missing something, but it seems like my only option is to use MCInstPrinter::getOpcodeName and compare strings. (Of course, I could iterate through the opcodes and build up a table of the ones I'm interested in to avoid string

...// Print 64-bit register names if 64-bit integer registers are available. // Otherwise, print 32-bit register names. @@ -391,7 +396,10 @@ static bool printAsmMRegister(X86AsmPrinter &P, const MachineOperand &MO, break; } - O << '%' << X86ATTInstPrinter::getRegisterName(Reg); + if (emit_pct) + O << '%'; + + O << X86ATTInstPrinter::getRegisterName(Reg); return false; } @@ -464,6 +472,7 @@ bool X86AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, case 'w': // Print HImode register case 'k': //...

...> - O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); > + O << '\t' << "mov"; > printSBitModifierOperand(MI, 6, O); > printPredicateOperand(MI, 4, O); > > O << '\t' << getRegisterName(Dst.getReg()) > - << ", " << getRegisterName(MO1.getReg()); > + << ", " << getRegisterName(MO1.getReg()) > + << ", " << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));; > > if (ARM_AM::g...

...oway <s at pahtak.org> wrote: > > On Oct 28, 2013, at 2:02 PM, Tyler Hardin <tghardin1 at catamount.wcu.edu> > wrote: > > > See the source here: > https://github.com/earl/llvm-mirror/blob/master/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp. > It looks like getRegisterName might do what you want, but I don't know > where it's coming from. (Whether it's a function or a member of a super > class. Hopefully, if it's a member, it's public.) > > Looks like X86ATTInstPrinter::getRegisterName() and > X86IntelInstPrinter::getRegisterName()...

...t? After ISEL, one of the instructions has another instruction folded into it, which looks like this t1: i32,i1,i1,i1,i1 = ADDRR TargetFrameIndex:i32<0>, MOVRI:i32,i1,i1 But during the 'Assembly Printer' pass, when emitting the assembly for ADDRR, the assertion at the beginning of getRegisterName() in XXXGenAsmWriter.inc fails because RegNo is 0. I'd like to know how that happened. Thanks. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20190213/9beb0835/attachment.html>

...-bit integer registers are > available. > // Otherwise, print 32-bit register names. > @@ -391,7 +396,10 @@ static bool printAsmMRegister(X86AsmPrinter &P, const > MachineOperand &MO, > break; > } > > - O << '%' << X86ATTInstPrinter::getRegisterName(Reg); > + if (emit_pct) > + O << '%'; > + > + O << X86ATTInstPrinter::getRegisterName(Reg); > return false; > } > > @@ -464,6 +472,7 @@ bool X86AsmPrinter::PrintAsmOperand(const MachineInstr > *MI, unsigned OpNo, > case 'w': //...

...// Print 64-bit register names if 64-bit integer registers are available. // Otherwise, print 32-bit register names. @@ -391,7 +396,10 @@ static bool printAsmMRegister(X86AsmPrinter &P, const MachineOperand &MO, break; } - O << '%' << X86ATTInstPrinter::getRegisterName(Reg); + if (EmitPercent) + O << '%'; + + O << X86ATTInstPrinter::getRegisterName(Reg); return false; } ~Craig On Wed, Feb 7, 2018 at 3:40 PM, David Woodhouse via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On Wed, 2018-02-07 at 23:30 +0000, Chandler Car...

On Wed, 2018-02-07 at 23:30 +0000, Chandler Carruth wrote: > This should go to llvm-commits as a proper review. Do you want to do > that David? Want someone on our end to pick it up? I'll attempt to add some test cases... -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/x-pkcs7-signature Size: 5213 bytes Desc: not available

...here in lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNo); if (Op.isReg()) { O << '%' << getRegisterName(Op.getReg()); } else if (Op.isImm()) { ... } else { assert(Op.isExpr() && "unknown operand kind in printOperand"); // HERE I remove the '$' to make it work O << '$' << *Op.getExpr(); } I hope someone is good in this thing! Than...

On Wed, 2018-02-07 at 13:16 -0800, Guenter Roeck wrote: > Here are my exact versions: >     llvm: 3afd566557f3 ("AMDGPU: Add 32-bit constant address space") >     clang: 848874aed95a ("[clang-format] Fix ObjC message arguments formatting.") OK, mine are slightly newer than that now, but I now get a working 64- bit defconfig build. It'll still break with any PV

Thanks for your reply Quentin. I do understand that the registers are allocated much later in the pipeline. I am assuming that the physical registers are allocated before MipsAsmPrinter class. I am doing something like if (MI->getOpcode() == Mips::OPCODE) { unsigned n = MI->getNumOperands(); for(unsigned i=0 ; i < n ; i++) { const MachineOperand &MO =

On 06/21/2010 08:21 PM, Eric Christopher wrote: > On Jun 21, 2010, at 2:56 AM, Patrick Marlier wrote: > > >> Hello, >> >> This bug affects all LLVM versions from 2.6 to trunk : >> http://llvm.org/bugs/show_bug.cgi?id=5081 >> >> The workaround I found is to add this : >> >> Index: lib/Target/X86/X86Instr64bit.td >>

...6/AsmPrinter/X86ATTInstPrinter.cpp > > void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, > raw_ostream &O) { > const MCOperand &Op = MI->getOperand(OpNo); > if (Op.isReg()) { > O << '%' << getRegisterName(Op.getReg()); > } else if (Op.isImm()) { > ... > } else { > assert(Op.isExpr() && "unknown operand kind in printOperand"); > // HERE I remove the '$' to make it work > O << '$' << *Op.getExpr(); > } > Hrm. Somethin...

On Wed, Feb 07, 2018 at 08:44:32PM +0000, David Woodhouse wrote: > On Wed, 2018-02-07 at 10:11 -0800, Guenter Roeck wrote: > > > On Wed, Feb 07, 2018 at 10:49:25AM +0000, David Woodhouse wrote: > > > Hm, please could we also have the %V asm constraint modifier? That > > > allows us to emit calls to the thunks from inline asm using the > > > register that the

...inter.cpp >> >> void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, >> raw_ostream&O) { >> const MCOperand&Op = MI->getOperand(OpNo); >> if (Op.isReg()) { >> O<< '%'<< getRegisterName(Op.getReg()); >> } else if (Op.isImm()) { >> ... >> } else { >> assert(Op.isExpr()&& "unknown operand kind in printOperand"); >> // HERE I remove the '$' to make it work >> O<< '$'<< *Op.getExpr();...

...Printer->printRegName(OS, LLVMRegister); } else { OS << Register; } } My current implementation of printRegName which I copied from other backends (X86, ARM and PowerPC) looks like this: void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { OS << getRegisterName(RegNo); } This will result in code like this .cfi_offset RA, -4 , instead of something like this: .cfi_offset 31, -4 -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110706/50c883c9/attachment.html>