Displaying 20 results from an estimated 81 matches for "getregisterinfo".
2013 Sep 25
2
[LLVMdev] Register scavenger and SP/FP adjustments
...eplaceFrameIndices) that is supposed to track
the SP/FP adjustment:
----------------------------------------
void PEI::replaceFrameIndices(MachineBasicBlock *BB,
MachineFunction &Fn, int &SPAdj) {
const TargetMachine &TM = Fn.getTarget();
assert(TM.getRegisterInfo() &&
"TM::getRegisterInfo() must be implemented!");
const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
bool StackGrowsDown =...
2013 Sep 26
0
[LLVMdev] Register scavenger and SP/FP adjustments
...t is supposed to track the SP/FP adjustment:
>
> ----------------------------------------
> void PEI::replaceFrameIndices(MachineBasicBlock *BB,
> MachineFunction &Fn, int &SPAdj) {
> const TargetMachine &TM = Fn.getTarget();
> assert(TM.getRegisterInfo() &&
> "TM::getRegisterInfo() must be implemented!");
> const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
> const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
> const TargetFrameLowering *TFI = TM.getFrameLowering();
> bool StackGr...
2006 Jul 02
2
[LLVMdev] Inserting move instruction
...signed src,
unsigned dst
)
{
MachineBasicBlock::iterator iter = mbb.getFirstTerminator();
const TargetRegisterClass *rc = mf.getSSARegMap()->getRegClass(dst);
const MRegisterInfo * reg_info = mf.getTarget().getRegisterInfo();
reg_info->copyRegToReg(mbb, iter, dst, src, rc);
}
But the getRegClass method seems to expect a virtual register. Could
someone fix this code for me? I could not find an example in the source of
LLVM.
Thank you very much,
Fernando
2013 Sep 26
2
[LLVMdev] Register scavenger and SP/FP adjustments
...the SP/FP adjustment:
>>
>> ----------------------------------------
>> void PEI::replaceFrameIndices(MachineBasicBlock *BB,
>> MachineFunction &Fn, int &SPAdj) {
>> const TargetMachine &TM = Fn.getTarget();
>> assert(TM.getRegisterInfo() &&
>> "TM::getRegisterInfo() must be implemented!");
>> const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
>> const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
>> const TargetFrameLowering *TFI = TM.getFrameLowering();
&g...
2006 Jul 02
2
[LLVMdev] Inserting move instruction
> On Sun, 2 Jul 2006, Fernando Magno Quintao Pereira wrote:
>
> > MachineBasicBlock::iterator iter = mbb.getFirstTerminator();
> > const TargetRegisterClass *rc = mf.getSSARegMap()->getRegClass(dst);
> > const MRegisterInfo * reg_info = mf.getTarget().getRegisterInfo();
> > reg_info->copyRegToReg(mbb, iter, dst, src, rc);
> > }
> >
> > But the getRegClass method seems to expect a virtual register. Could
> > someone fix this code for me? I could not find an example in the source of
> > LLVM.
>
> You can't do it...
2013 Sep 26
0
[LLVMdev] Register scavenger and SP/FP adjustments
...>>>
>>> ----------------------------------------
>>> void PEI::replaceFrameIndices(MachineBasicBlock *BB,
>>> MachineFunction &Fn, int &SPAdj) {
>>> const TargetMachine &TM = Fn.getTarget();
>>> assert(TM.getRegisterInfo() &&
>>> "TM::getRegisterInfo() must be implemented!");
>>> const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
>>> const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
>>> const TargetFrameLowering *TFI = TM.getFrameLo...
2006 Jul 02
0
[LLVMdev] Inserting move instruction
On Sun, 2 Jul 2006, Fernando Magno Quintao Pereira wrote:
> MachineBasicBlock::iterator iter = mbb.getFirstTerminator();
> const TargetRegisterClass *rc = mf.getSSARegMap()->getRegClass(dst);
> const MRegisterInfo * reg_info = mf.getTarget().getRegisterInfo();
> reg_info->copyRegToReg(mbb, iter, dst, src, rc);
> }
>
> But the getRegClass method seems to expect a virtual register. Could
> someone fix this code for me? I could not find an example in the source of
> LLVM.
You can't do it with this information. In some higher...
2013 Sep 26
1
[LLVMdev] Register scavenger and SP/FP adjustments
...t;>> ----------------------------------------
>>>> void PEI::replaceFrameIndices(MachineBasicBlock *BB,
>>>> MachineFunction &Fn, int &SPAdj) {
>>>> const TargetMachine &TM = Fn.getTarget();
>>>> assert(TM.getRegisterInfo() &&
>>>> "TM::getRegisterInfo() must be implemented!");
>>>> const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
>>>> const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
>>>> const TargetFrameLowering *TFI...
2014 Oct 13
2
[LLVMdev] Problem of stack slot coloring
...s transformation pass relies on the LiveStack analysis pass.
How, when checking the source code, it seems the LiveStack analysis has not
been implemented, since the code was found in LiveStackAnalysis.cpp:
*bool LiveStacks::runOnMachineFunction(MachineFunction &MF) {*
* TRI = MF.getTarget().getRegisterInfo();*
* // FIXME: No analysis is being done right now. We are relying on the*
* // register allocators to provide the information.*
* return false;*
*}*
And I found the greedy register allocator did nothing to fill the
LiveStackAnalysis::*S2IMap, *which is critical for the stack slot coloring.
Fu...
2006 Aug 14
2
[LLVMdev] Folding instructions
...m getting errors
that
I don't know how to fix. Could someone tell me which steps should I take
in order
to correctly fold memory operands? The code that I am using is:
const TargetMachine & target_machine =
this->machine_function->getTarget();
const MRegisterInfo *ri = target_machine.getRegisterInfo();
MachineInstr * fmi = ri->foldMemoryOperand(mi, u, slot);
if(fmi) {
numFolded++;
MachineBasicBlock * mbb = mi->getParent();
this->vrm->virtFolded(v_reg, mi, u, fmi);
//std::cerr << "Folding " << NeatPrint::mi2string(*mi,
*this->machine_function) &l...
2006 Aug 14
0
[LLVMdev] Folding instructions
...ow how to fix. Could someone tell me which steps should I
> take
> in order
> to correctly fold memory operands? The code that I am using is:
>
> const TargetMachine & target_machine =
> this->machine_function->getTarget();
> const MRegisterInfo *ri = target_machine.getRegisterInfo();
> MachineInstr * fmi = ri->foldMemoryOperand(mi, u, slot);
> if(fmi) {
> numFolded++;
> MachineBasicBlock * mbb = mi->getParent();
> this->vrm->virtFolded(v_reg, mi, u, fmi);
> //std::cerr << "Folding " << NeatPrint::mi2string(*mi,...
2006 Jul 02
0
[LLVMdev] Inserting move instruction
...code here:
void PhiDeconstruction_Fer::add_move
(MachineBasicBlock & mbb, unsigned src, unsigned
dst) {
MachineBasicBlock::iterator iter = mbb.getFirstTerminator();
const MRegisterInfo * reg_info =
this->machine_function->getTarget().getRegisterInfo();
// TODO: verify if does not causes incorrect allocation:
for(MRegisterInfo::regclass_iterator rcii = reg_info->regclass_begin(),
rcie = reg_info->regclass_end(); rcii != rcie; ++rcii) {
if( (*rcii)->contains(dst) ) {
rc = * rcii;...
2012 Nov 29
0
[LLVMdev] [llvm-commits] RFC: Merge branches/R600 into TOT for 3.2 release
...·»·······»·······»·······branchDL);
No tabs, please.
+AMDGPUCFGStructurizer::AMDGPUCFGStructurizer(char &pid, TargetMachine &tm
+ )
+: MachineFunctionPass(pid), TM(tm), TII(tm.getInstrInfo()),
+ TRI(static_cast<const AMDGPURegisterInfo *>(tm.getRegisterInfo())
+ ) {
+}
Both right parentheses should be on previous lines.
+}; //end of class AMDGPUCFGPrepare
In general I don't see "end of class" and "end of function" comments
in LLVM, just namespaces.
+// The AMDGPUCypressDevice is similiar to the AMDGPUEvergreenDevice,
exc...
2012 Oct 06
2
[LLVMdev] Pairing Registers on a Target Similar to Mips?
...MachineBasicBlock::iterator
I) {
unsigned DstReg = I->getOperand(0).getReg();
unsigned SrcReg = I->getOperand(1).getReg();
const MCInstrDesc& Dmfc1Tdd = TII->get(MIPS::DMFC1);
DebugLoc dl = I->getDebugLoc();
const uint16_t* SubReg =
TM.getRegisterInfo()->getSubRegisters(SrcReg);
BuildMI(MBB, I, dl, Dmfc1Tdd, DstReg).addReg(*SubReg);
}
Finally, I want to add the rule to ISelLowering to actually use these
rules. Under the CCValAssign::Full case in the LowerCall function, here is
the old code:
SDValue Lo = DAG.getNode(MIPS...
2014 Oct 14
2
[LLVMdev] Problem of stack slot coloring
...gt; > How, when checking the source code, it seems the LiveStack analysis
> > has not been implemented, since the code was found in
> > LiveStackAnalysis.cpp:
> >
> >
> > bool LiveStacks::runOnMachineFunction(MachineFunction &MF) {
> > TRI = MF.getTarget().getRegisterInfo();
> > // FIXME: No analysis is being done right now. We are relying on the
> > // register allocators to provide the information.
> > return false;
> > }
> >
> >
> > And I found the greedy register allocator did nothing to fill the
> > LiveStackAnaly...
2006 Aug 14
2
[LLVMdev] Folding instructions
...truction. If we can do this, we don't need to
// insert spill code.
const TargetMachine & target_machine =
this->machine_function->getTarget();
const MRegisterInfo *ri =
target_machine.getRegisterInfo();
MachineInstr * fmi =
ri->foldMemoryOperand(mi, u, slot);
if(fmi) {
numFolded++;
MachineBasicBlock * mbb = mi->getParent();
------> //this->vrm->virtFolded(v_reg, mi, u, fmi);
ks...
2011 Oct 11
1
[LLVMdev] Expected behavior of eliminateFrameIndex() on dbg_value machine instructions
...t::constructVariableDIE is trying to do:
if (const MachineInstr *DVInsn = DV->getMInsn()) {
bool updated = false;
if (DVInsn->getNumOperands() == 3) {
if (DVInsn->getOperand(0).isReg()) {
const MachineOperand RegOp = DVInsn->getOperand(0);
const TargetRegisterInfo *TRI = Asm->TM.getRegisterInfo();
if (DVInsn->getOperand(1).isImm() &&
TRI->getFrameRegister(*Asm->MF) == RegOp.getReg()) {
unsigned FrameReg = 0;
const TargetFrameLowering *TFI = Asm->TM.getFrameLowering();
int Offset =...
2007 Feb 14
2
[LLVMdev] Linux/ppc backend
...if (Subtarget.isMachoABI()){
return Defs_Macho;
} else {
return Defs_ELF;
}
}
GPRClass::iterator
GPRClass::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const MRegisterInfo *RI = TM.getRegisterInfo();
const PPCSubtarget &Subtarget = TM.getSubtarget<PPCSubtarget>();
GPRClass::iterator I;
if (Subtarget.isMachoABI()) {
I = Defs_Macho + (sizeof(Defs_Macho)/sizeof(unsigned));
} else {
I = Defs_ELF + (sizeof(Defs_ELF)/sizeof(unsigned));
}...
2012 Oct 09
0
[LLVMdev] Pairing Registers on a Target Similar to Mips?
...rator
> I) {
> unsigned DstReg = I->getOperand(0).getReg();
> unsigned SrcReg = I->getOperand(1).getReg();
> const MCInstrDesc& Dmfc1Tdd = TII->get(MIPS::DMFC1);
>
> DebugLoc dl = I->getDebugLoc();
> const uint16_t* SubReg =
> TM.getRegisterInfo()->getSubRegisters(SrcReg);
>
> BuildMI(MBB, I, dl, Dmfc1Tdd, DstReg).addReg(*SubReg);
> }
>
>
If I understand correctly what you are trying to do, DMFC1 is supposed to
read a f64 register and copy it to a pair of i32 registers. This code
doesn't seem to be doing tha...
2011 Jan 18
2
[LLVMdev] Dwarf info for byref register variables
Two functions in DwarfDebug, addBlockByrefAddress() and
addComplexAddress(), contain this snippet of code:
// Decode the original location, and use that as the start of the byref
// variable's location.
const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo();
unsigned Reg = RI->getDwarfRegNum(Location.getReg(), false);
DIEBlock *Block = new (DIEValueAllocator) DIEBlock();
if (Location.isReg()) {
if (Reg < 32)
addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_reg0 + Reg);
else {
Reg...