search for: getregallocationhint

...AM, Luo, Yuanke wrote: > > Hi Hal, > > Thank you for the ideas that help us to improve the design, and sorry > for replying late. There is something I am not able to figure out and > there some special trait for tile RA. > You're quite welcome. > 1.X86RegisterInfo::getRegAllocationHints can tell RA which physical > register is preferred, but it can’t force RA to just allocate the > hinted register. If the hinted register is not meet, RA would allocate > other register. > I addressed this below, but I could have been clearer. Like SystemZRegisterInfo::getRegAlloca...

...on-overlapping live ranges, etc.), but with an additional constraint: once a physical register has been used with some particular tile shape, it cannot be assigned to any other tile shape. I think that the current infrastructure can support this as follows:  1. Add an override X86RegisterInfo::getRegAllocationHints. Like SystemZRegisterInfo::getRegAllocationHints does sometimes, when hinting the tile registers, the function will return true (to indicate a hard constraint). As registers are assigned in RegAllocGreedy, getRegAllocationHints is called for each virtual register. For virtual tile registers,...

...el discussion. On 9/4/20 3:37 AM, Luo, Yuanke wrote: Hi Hal, Thank you for the ideas that help us to improve the design, and sorry for replying late. There is something I am not able to figure out and there some special trait for tile RA. You're quite welcome. 1. X86RegisterInfo::getRegAllocationHints can tell RA which physical register is preferred, but it can't force RA to just allocate the hinted register. If the hinted register is not meet, RA would allocate other register. I addressed this below, but I could have been clearer. Like SystemZRegisterInfo::getRegAllocationHints does som...

Hi all, I was wondering about whether the PBQP register allocator is likely to be maintained in the future. It's proving to be a nice way to encode some instruction encoding constraints for an out-of-tree backend we have, but there's concern about it being abandoned or bitrotting in the future. Also, if PBQP is likely to lapse out of regular maintenance in the future, is there a simple

I just updated register allocation hinting mechanism to be more flexible and hopefully easier to use. If you have an out-of-tree target that was overriding the TRI::ResolveRegAllocHint() or TRI::getRawAllocationOrder() functions, you should switch it to using the new TRI::getRegAllocationHints() function instead. See the ARM target for an example. Zino, I believe the new hints are powerful enough to improve ldm/stm formation on ARM. Were you interested in working on that? /jakob

Hi Hal, The proposal is attractive to me, but there is something I still can't figure out. Let's take below MIR as an example. We assume we have 256 register classes (vtile1x1, vtile1x2, ..., tile16x16). 1. After instruction selection, the pseudo AMX instruction is generated. The name of pseudo instructions have 'P' prefix. Now all the AMX pseudo instruction take vtile as