search for: getreg

...pass over the instructions and compute spill // weights, coalesce virtual registers and remove identity moves ... for (unsigned i = 0; i < mii->getNumOperands(); ++i) { const MachineOperand& mop = mii->getOperand(i); if (mop.isRegister() && mop.getReg() && MRegisterInfo::isVirtualRegister(mop.getReg())) { // replace register with representative register unsigned reg = rep(mop.getReg()); mii->SetMachineOperandReg(i, reg); LiveInterval &RegInt = getInterval(reg);...

...instructions have. For example, on many architectures, immediates are limited to 13 bits or some other small number. Also, for virtual regsiters, there is no context to hold the mapping of Value*'s -> vregs: this is what the instruction selector is about. I recommend taking a look at the getReg(*) methods in the X86 instruction selector. The basic code generation stage for an add, boiled down to its simplest form, basically looks like this: void visitAdd(BinaryOperator &B) { unsigned Op0Reg = getReg(B.getOperand(0)); unsigned Op1Reg = getReg(B.getOperand(1)); unsigned DestReg...

...al register. 2. Why SSARegMap is called this way. As far as I can see, it's does not implement any mapping, it simply allocates registers given a register class. 3. Maybe, the allocation of virtual registers for Value* should be made more reusable. The X86 backend has the code for that in getReg method in InstSelectSimple.cpp which: - uses SSARegMap instance - keeps internal Value* -> register mapping - copies constants into register when needed At least first two things will be necessary for my backend too. I start to wonder if it makes sense to make a "BasicInstructi...

...Loc DL = MI.getDebugLoc(); MachineOperand& reg1 = MI.getOperand(0); MachineOperand& reg2 = MI.getOperand(1); MachineOperand& reg3 = MI.getOperand(2); if(reg1.isReg() && reg2.isReg() && reg3.isReg()){ if((reg1.getReg()-8)%4 == (reg3.getReg()-8)%4){ MachineBasicBlock::instr_iterator NII = std::next(II); //conflict if reg1 and reg3 are in same bank errs() << "Conflict: "; printOp(opcode); errs() << " has &...

...3 = MI->getOperand(3); - O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); + O << '\t' << "mov"; printSBitModifierOperand(MI, 6, O); printPredicateOperand(MI, 4, O); O << '\t' << getRegisterName(Dst.getReg()) - << ", " << getRegisterName(MO1.getReg()); + << ", " << getRegisterName(MO1.getReg()) + << ", " << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));; if (ARM_AM::getSORegShOp(MO...

Cool, that worked. New patch attached... Cheers, Gary Evan Cheng wrote: > Just cast both values to const TargetRegisterClass*. > > Evan > > On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > > Evan Cheng wrote: > > > How about? > > > > > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > > > &PPC:G8RCRegClass; > > > unsigned...

...Operand(3); CC = (INSTCC::CondCodes)MI->getOperand(3).getImm(); // Here I want to get the destination register of SET_CC instruction and place it as the first addReg TODO(Get setcc destination register); BuildMI(BB, TII.get(INST::CMOVLOG_32),Dst.getReg()).addReg(CCFlag.getImm()).addReg(T rueVal.getReg()).addReg(FalseVal.getReg()); } break; case INST::SET_CC: { MachineOperand Dst = MI->getOperand(0); MachineOperand LHS = MI->getOperand(1); MachineOper...

...{ if(TII.isReMaterializablePossible(*DefMI, aa)) return false; DEBUG(dbgs() << " ComplexRemat MI: " << *DefMI); for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = DefMI->getOperand(i); if (!MO.isReg() || !MO.getReg() || !MO.readsReg()) continue; if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { if (MRI.isConstantPhysReg(MO.getReg(), *DefMI->getParent()->getParent())) continue; //If not constant then check its def if(depth > 6) return false;...

...rs. BB->addSuccessor(copy0MBB); BB->addSuccessor(sinkMBB); // Emit the right instruction according to the type of the operands compared if (isFPCmp) BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); else BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) .addReg(Mips::ZERO).addMBB(sinkMBB); // copy0MBB: // %FalseValue = ... // # fallthrough to sinkMBB BB = copy0MBB; // Update machine-CFG edges BB->addSuccessor(sinkMBB); // sinkMBB: // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]...

...want to emit the following the following instruction sequence: cmp r0, r1 moveq r2, #1 To implement this, I first emit a compare instruction and then I'm trying to emit the conditional move, which is failing. BuildMI(&MBB, DL, TII->get(ARM::CMPrr)) .addReg(MI.getOperand(1).getReg()) .addReg(MI.getOperand(2).getReg()) .addImm(ARMCC::EQ); BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVr), MI.getOperand(0).getReg()) .addImm(ARMCC::EQ) .addImm(1) .addReg(0); // 's' bit But with the last condit...

On Jun 22, 2011, at 9:00 AM, Renato Golin wrote: > On 22 June 2011 16:50, Jim Grosbach <grosbach at apple.com> wrote: >>> This sounds like a dead end as newer binutils are GPLv3. >> >> Yeah, that's definitely a very real concern and a big motivation to get the MC based asm parser whipped into usable shape. We're much more in control of our own destiny then.

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > > Cheers, > Gary >

...rent(); - MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); - MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); - unsigned SelectPred = MI->getOperand(4).getImm(); - BuildMI(BB, TII->get(PPC::BCC)) - .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); - F->insert(It, copy0MBB); - F->insert(It, sinkMBB); - // Update machine-CFG edges by transferring all successors of the current - // block to the new block which will contain the Phi node for the select. - sinkMBB->transferSuccessors(BB); - // Next, add the true...

...does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: >>> Evan Cheng wrote: >>>> How about? >>>> >>>> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >>>> &PPC:G8RCRegClass;...

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > >...

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting thi...

You need to insert new basic blocks and update CFG to accomplish this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See

...m :) I attached an updated patch which creates a virtual register instead of using R0. How does this look? Cheers, Gary Dan Gohman wrote: > PPCTargetLowering::EmitInstrWithCustomInserter has a reference > to the current MachineFunction for other purposes. Can you use > MachineFunction::getRegInfo instead? > > Dan > > On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > > Would it be acceptable to change MachineInstr::getRegInfo > > from private to public so I can use it from > > PPCTargetLowering::EmitInstrWithCustomInserter? > > > > Cheers, >...

Would it be acceptable to change MachineInstr::getRegInfo from private to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter? Cheers, Gary Evan Cheng wrote: > Look for createVirtualRegister. These are examples in > PPCISelLowering.cpp. > > Evan > On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > > >...

Chris Lattner wrote: > On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > > $label), > > "cmpw $rA, $rB\n\tbne- La${label}_exit", > > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > > $label)]>; > > } > > > > ...and