search for: getrawallocationorder

...&& "Reserved register assignment"); Indeed there is a case where PhysReg may be a reserved physical register. Specificially, RegAllocPBQP::finalizeAlloc() may select a physical register thusly: const TargetRegisterClass &RC = *MRI.getRegClass(LI.reg); PReg = RC.getRawAllocationOrder(MF).front(); ... VRM.assignVirt2Phys(LI.reg, PReg); The documentation for TargetRegisterClass::getRawAllocationOrder() notes that the collection may include reserved registers. So it seems that the PBQP allocator may insert a reserve physical register into the VirtRegMap. I'm not...

Hi all, I would like to know if XXXInstrInfo.td or other td files should be the right place to specify Src Reg and Dest Reg in one instruction can't be the same. If so, could you give an example on that? Thanks! Regards, chenwj -- Wei-Ren Chen (陳韋任) Computer Systems Lab, Institute of Information Science, Academia Sinica, Taiwan (R.O.C.) Tel:886-2-2788-3799 #1667 Homepage:

Hi Wei-Ren, I don't think you can model it with Constraints in td files. You may try to put a regalloc hint in src and dst operands of the instructions you are interested. See getRawAllocationOrder(), ResolveRegAllocHint() and UpdateRegAllocHint() hooks in TargetRegisterInfo. ARM has good examples on how to implements them. Ivan On 13/07/2012 09:28, 陳韋任 (Wei-Ren Chen) wrote: > Hi all, > > I would like to know if XXXInstrInfo.td or other td files should be > the right place...

...n formats. It was a huge work. I am going > to compile and run it now. We have done the similar work[1] on this topic by gcc and we have start migrate our platform to LLVM. In my experience, you need to take care the follow part: * ARMBaseRegisterInfo::getRegPressureLimit * ARMBaseRegisterInfo::getRawAllocationOrder * CalleeSavedRegs * ARMFrameLowering::emitPrologue [1] Doubling the Number of Registers on ARM Processors http://aces.snu.ac.kr/interact-16/papers/interact-16-paper-1.pdf

I almost change all the instruction formats. It was a huge work. I am going to compile and run it now. Best Regards, A. Yazdanbakhsh >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> PhD. Student School of Electrical and Computer Engineering University of Wisconsin-Madison E-mail: yazdanbakhsh

...he code that gets a preg for a given vreg. Previously,you gave me code that takes into account the "allocation order" and the "reserved regs", including the following: BitVector reservedRegs = TRI->getReservedRegs(Fn); ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn); ArrayRef<uint16_t>::iterator rItr = rawOrder.begin(); while (rItr != rawOrder.end()) { while (rItr != rawOrder.end() && reservedRegs.test(*rItr)) { ++rItr; } As I recall, this prevented some failed assertion. Why has that c...

...vreg in function bar. Loading/saving RBP should be managed by the stack frame setup/teardown code. If it doesn't already, your allocator should filter out reserved registers (See MachineRegisterInfo::isReserved(unsigned preg)) when assigning physregs. ArrayRef<MCPhysReg> pregs = TRC->getRawAllocationOrder(&MF); for (int i = 0; i < pregs.size(); ++i) { if (MRI->isReserved(pregs[i])) continue; // use preg... } You could also use the AllocationOrder class to simplify the task of finding valid pregs, though it does require you to use VirtRegMap. If you are already checking the reserv...

...t the appropriate TargetRegisterClass (needed to call > CreateSpillStackObject). Should I instead be generating code to save > register EBP at the start of scinstal, restoring it at the end of that > function? > > Susan > > > > ArrayRef<MCPhysReg> pregs = TRC->getRawAllocationOrder(&MF); > for (int i = 0; i < pregs.size(); ++i) { > if (MRI->isReserved(pregs[i])) > continue; > // use preg... > } > > You could also use the AllocationOrder class to simplify the task of > finding valid pregs, though it does require you to use VirtRegMap....

...isterClass > (needed to call CreateSpillStackObject). Should I instead be > generating code to save register EBP at the start of scinstal, > restoring it at the end of that function? > > Susan > > >> >> ArrayRef<MCPhysReg> pregs = TRC->getRawAllocationOrder(&MF); >> for (int i = 0; i < pregs.size(); ++i) { >> if (MRI->isReserved(pregs[i])) >> continue; >> // use preg... >> } >> >> You could also use the AllocationOrder class to simplify the task >> of finding...

I just updated register allocation hinting mechanism to be more flexible and hopefully easier to use. If you have an out-of-tree target that was overriding the TRI::ResolveRegAllocHint() or TRI::getRawAllocationOrder() functions, you should switch it to using the new TRI::getRegAllocationHints() function instead. See the ARM target for an example. Zino, I believe the new hints are powerful enough to improve ldm/stm formation on ARM. Were you interested in working on that? /jakob

Hi Susan, Jakob just pointed me to 'MachineOperand::substPhysReg(unsigned preg, const TargetRegisterInfo& TRI)'. That substitutes the given physreg for a virtreg operand, taking the subregister index into account. That is what my examples have been doing manually. Using substPhysReg would allow you to tidy the Gcra code up slightly. - Lang. On Thu, Nov 15, 2012 at 11:21 AM, Lang

Thanks Jakob. I should have mentioned that earlier. :) When you see mismatched sizes on operands it's a fair bet that the subreg rewriting has gone wrong. I should have pulled that entirely out of the preg search loop in the previous example. Fixed version attached. - Lang. -------------- next part -------------- An HTML attachment was scrubbed... URL:

...filter out any reserved registers). I've attached a test-case > where I do this somewhat manually. In short: > > int regClass = MRI->getRegClass(vreg)->getID(); > const TargetRegisterClass *trc = TRI->getRegClass(regClass); > ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn); > ArrayRef<uint16_t>::iterator rItr = rawOrder.begin(); > while (reservedRegs.test(*rItr)) > ++rItr; > preg = *rItr; > > Alternatively, you could use the AllocationOrder class > (lib/CodeGen/AllocationOrder.h). This has the benefit of considering > register hin...

...(and as an added headache filter out any reserved registers). I've attached a test-case where I do this somewhat manually. In short: int regClass = MRI->getRegClass(vreg)->getID(); const TargetRegisterClass *trc = TRI->getRegClass(regClass); ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn); ArrayRef<uint16_t>::iterator rItr = rawOrder.begin(); while (reservedRegs.test(*rItr)) ++rItr; preg = *rItr; Alternatively, you could use the AllocationOrder class (lib/CodeGen/AllocationOrder.h). This has the benefit of considering register hints for improved coalescing too. It does,...

.... I've attached a test-case where I do this >> somewhat manually. In short: >> >> int regClass = MRI->getRegClass(vreg)->getID(); >> const TargetRegisterClass *trc = TRI->getRegClass(regClass); >> ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn); >> ArrayRef<uint16_t>::iterator rItr = rawOrder.begin(); >> while (reservedRegs.test(*rItr)) >> ++rItr; >> preg = *rItr; >> >> Alternatively, you could use the AllocationOrder class >> (lib/CodeGen/AllocationOrder.h). Th...

...rved registers). I've attached a test-case >> where I do this somewhat manually. In short: >> >> int regClass = MRI->getRegClass(vreg)->getID(); >> const TargetRegisterClass *trc = TRI->getRegClass(regClass); >> ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn); >> ArrayRef<uint16_t>::iterator rItr = rawOrder.begin(); >> while (reservedRegs.test(*rItr)) >> ++rItr; >> preg = *rItr; >> >> Alternatively, you could use the AllocationOrder class >> (lib/CodeGen/AllocationOrder.h). This has the benefit of c...

...filter out any reserved registers). I've attached a > test-case where I do this somewhat manually. In short: > > int regClass = MRI->getRegClass(vreg)->getID(); > const TargetRegisterClass *trc = TRI->getRegClass(regClass); > ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn); > ArrayRef<uint16_t>::iterator rItr = rawOrder.begin(); > while (reservedRegs.test(*rItr)) > ++rItr; > preg = *rItr; > > Alternatively, you could use the AllocationOrder class > (lib/CodeGen/AllocationOrder.h). This has the benefit of considering > register hi...

...ched a test-case where I do this somewhat manually. In short: >>> >>> int regClass = MRI->getRegClass(vreg)->getID(); >>> const TargetRegisterClass *trc = TRI->getRegClass(regClass); >>> ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn); >>> ArrayRef<uint16_t>::iterator rItr = rawOrder.begin(); >>> while (reservedRegs.test(*rItr)) >>> ++rItr; >>> preg = *rItr; >>> >>> Alternatively, you could use the AllocationOrder class >...

...mewhat manually. In >>>> short: >>>> >>>> int regClass = MRI->getRegClass(vreg)->getID(**); >>>> const TargetRegisterClass *trc = TRI->getRegClass(regClass); >>>> ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn)**; >>>> ArrayRef<uint16_t>::iterator rItr = rawOrder.begin(); >>>> while (reservedRegs.test(*rItr)) >>>> ++rItr; >>>> preg = *rItr; >>>> >>>> Alternatively, you could use the...

Hi Susan, Sorry for the delayed response. Thanks for the test cases - I'm looking in to this now. - Lang. On Mon, Nov 5, 2012 at 2:58 PM, Susan Horwitz <horwitz at cs.wisc.edu> wrote: > Hi Lang, > > I looked more into one of the problems I'm now having, and I've attached 3 > files: > > Gcra.cpp is like your version except that for two specific vregs it uses