search for: getpostindexedaddresspart

Hi, I'm trying to enable the pre-decrementing and post-incrementing based addressing modes for my target. So far without any success :( I enabled these modes in my TargetLowering class using setIndexedLoadAction and setIndexedStoreAction calls. I also defined getPreIndexedAddressParts and getPostIndexedAddressParts. And I can see that DAGCombiner::CombineToPostIndexedLoadStore is invoked. But this function never does any replacements and very seldomly invoke getPostIndexedAddressParts and so on, even in those situations where I would assume it. For example, it does not use these modes for the code like: voi...

Hi Chris, --- Chris Lattner <sabre at nondot.org> wrote: > On Wed, 29 Nov 2006, Roman Levenstein wrote: > > Thanks, this is a good idea. > > > > But I cannot figure out how to make a machine function pass run > > _BEFORE_ the RA. I guess I'm missing something very obvious. > > In your target's TargetMachine::addInstSelector method, add it to the

...u seem to be aware, LLVM has patterns specifically to match pre/post increment loads and stores (post_store). In your *ISelLowering.cpp file, you'll need to call setIndexedLoadAction(ISD::POST_INC, <type>, Legal), and the same for setIndexedStoreAction. Then you'll need to implement a getPostIndexedAddressParts function in that same file (you can look in the ARM backend for an example). If you can select your indirect moves using TableGen patterns, then you can probably use the post_store pattern. -Hal > > Thanks and regards, > Shashidhar > _______________________________________________...

Hi, We have an architecture where the indirect move instruction implicitly increments the pointer value after the move. We have Instruction format and pattern for this type of instructions. How to encode the information that the pointer is incremented? Thanks and regards, Shashidhar

...u seem to be aware, LLVM has patterns specifically to match pre/post increment loads and stores (post_store). In your *ISelLowering.cpp file, you'll need to call setIndexedLoadAction(ISD::POST_INC, <type>, Legal), and the same for setIndexedStoreAction. Then you'll need to implement a getPostIndexedAddressParts function in that same file (you can look in the ARM backend for an example). If you can select your indirect moves using TableGen patterns, then you can probably use the post_store pattern. > > -Hal > >> Thanks and regards, >> Shashidhar >> ____________________________...

...to match > > pre/post increment loads and stores (post_store). In your > > *ISelLowering.cpp file, you'll need to call > > setIndexedLoadAction(ISD::POST_INC, <type>, Legal), and the same > > for setIndexedStoreAction. Then you'll need to implement a > > getPostIndexedAddressParts function in that same file (you can > > look in the ARM backend for an example). If you can select your > > indirect moves using TableGen patterns, then you can probably use > > the post_store pattern. > > > > -Hal > > > >> Thanks and regards, > &g...

Hi all, On behalf of Andes Technology Corp, I am proposing a backend targeting the NDS32 V3 ISA. NDS32 V3 ISA is a 16/32 bit mixed instruction set architecture that developed By AndesTech. You can find more information at the Andes website <http://www.andestech.com/>, and reference AndeStar ISA Manual (V3 ISA) from document download page <http://www.andestech.com/product.php?cls=9>.

...gt;> pre/post increment loads and stores (post_store). In your >>> *ISelLowering.cpp file, you'll need to call >>> setIndexedLoadAction(ISD::POST_INC, <type>, Legal), and the same >>> for setIndexedStoreAction. Then you'll need to implement a >>> getPostIndexedAddressParts function in that same file (you can >>> look in the ARM backend for an example). If you can select your >>> indirect moves using TableGen patterns, then you can probably use >>> the post_store pattern. >>> >>> -Hal >>> >>>> Thank...