search for: getphys

Hey all, I've found a bug in either the PBQP register allocator or in VirtRegRewriter. I'm observing this assertion in VirtRegRewriter::rewrite() fail: unsigned VirtReg = MO.getReg(); unsigned PhysReg = VRM->getPhys(VirtReg); ... assert(!MRI->isReserved(PhysReg) && "Reserved register assignment"); Indeed there is a case where PhysReg may be a reserved physical register. Specificially, RegAllocPBQP::finalizeAlloc() may select a physical register thusly: const Target...

...he spill code handling inside selectOrSplit() (ignoring some control logic): for (LiveIntervals::const_iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) { unsigned VirtReg = I->first; if ((TargetRegisterInfo::isVirtualRegister(VirtReg)) && (VRM->getPhys(VirtReg) == REG_Y)) { LiveInterval &LI = LIS->getInterval(VirtReg); unassign(LI, REG_Y); enqueue(&LI); } } RegClassInfo.runOnMachineFunction(VRM->getMachineFunction()); // update reserve reglist So similar to what's done in LRE_WillShrinkVirtReg(), it...

...e = li_->end(); i != e; ++i) { LiveInterval &cur = *i->second; unsigned Reg = 0; bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg); if (isPhys) Reg = cur.reg; else if (vrm_->isAssignedReg(cur.reg)) Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg)); if (!Reg) continue; // Ignore splited live intervals. if (!isPhys && vrm_->getPreSplitReg(cur.reg)) continue; for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end(); I != E; ++I) { const LiveRange &LR = *I;...

...// Each valnum may have its own remat id. 00989 ReMatIds[VNI->id] = vrm.assignVirtReMatId(NewVReg); Linear scan dutifully assigns %reg1631 to AL. Then SimpleSpiller runs and does this: 00261 unsigned VirtReg = MO.getReg(); 00262 unsigned PhysReg = VRM.getPhys(VirtReg); 00263 if (!VRM.isAssignedReg(VirtReg)) { 00264 int StackSlot = VRM.getStackSlot(VirtReg); Well, according to VRM, %reg1631 is NOT assigned to a register (because it has a remat id) even though linear scan assigned it one. VRM then returns garbage as the stack...

...signed LIReg = L.reg; if (!MRegisterInfo::isVirtualRegister(LIReg) || LIReg == VReg) continue; // **** Check to see if the physreg we assigned conflicts with something // **** else. If so, that thing has to live in memory too. if (VRM->hasPhys(LIReg) && VRM->getPhys(LIReg) == PReg && !VRM->hasStackSlot(LIReg) && Added[I]->overlaps(L)) VRM->assignVirt2StackSlot(LIReg); } } The two points I want to talk about are noted by the **** comments. The first takes a newly-created live interval to represent the lifetime...

...tOrSplit() (ignoring some control logic): > > for (LiveIntervals::const_iterator I = LIS->begin(), E = LIS->end(); I != E; > ++I) > { > unsigned VirtReg = I->first; > if ((TargetRegisterInfo::isVirtualRegister(VirtReg)) > && (VRM->getPhys(VirtReg) == REG_Y)) > { > LiveInterval &LI = LIS->getInterval(VirtReg); > unassign(LI, REG_Y); > enqueue(&LI); > } > } > RegClassInfo.runOnMachineFunction(VRM->getMachineFunction()); // update reserve reglist > > So similar to wh...

On Nov 29, 2011, at 10:24 AM, Borja Ferrer wrote: > Yes, I want the register to be allocatable when there are no stack frames used in the function so it can be used for other purposes. In fact, I looked at how other backends solve this problem, but they are all too conservative by always reserving the register which in my case it is not a good solution because of the performance impact of not

...remat id. > 00989 ReMatIds[VNI->id] = vrm.assignVirtReMatId(NewVReg); > > Linear scan dutifully assigns %reg1631 to AL. Then SimpleSpiller > runs and > does this: > > 00261 unsigned VirtReg = MO.getReg(); > 00262 unsigned PhysReg = VRM.getPhys(VirtReg); > 00263 if (!VRM.isAssignedReg(VirtReg)) { > 00264 int StackSlot = VRM.getStackSlot(VirtReg); > > Well, according to VRM, %reg1631 is NOT assigned to a register > (because it has > a remat id) even though linear scan assigned it one. VRM then...

Yes, I want the register to be allocatable when there are no stack frames used in the function so it can be used for other purposes. In fact, I looked at how other backends solve this problem, but they are all too conservative by always reserving the register which in my case it is not a good solution because of the performance impact of not having this register available. I find very interesting

...!MRegisterInfo::isVirtualRegister(LIReg) || LIReg == > VReg) continue; > > // **** Check to see if the physreg we assigned conflicts > with something > // **** else. If so, that thing has to live in memory too. > if (VRM->hasPhys(LIReg) && VRM->getPhys(LIReg) == PReg && > !VRM->hasStackSlot(LIReg) && Added[I]->overlaps(L)) > VRM->assignVirt2StackSlot(LIReg); > } > } > > The two points I want to talk about are noted by the **** > comments. The first > takes a newly-created...

On Jan 13, 2009, at 12:27 AM, Roman Levenstein <romix.llvm at googlemail.com > wrote: > 2009/1/13 Evan Cheng <echeng at apple.com>: >> >> On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: >> >>> bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1: >>> Predecessors according to CFG: 0x8fdac90 (#0) >>> %R0<def> = MOVi 0, 14, %reg0,

2009/1/13 Evan Cheng <echeng at apple.com>: > > On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: > >> bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1: >> Predecessors according to CFG: 0x8fdac90 (#0) >> %R0<def> = MOVi 0, 14, %reg0, %reg0 >> *** STR %LR<kill>, %R0<kill>, %reg0, 0, 14, %reg0, Mem:ST(4,4) >> [0x8fc2d68 + 0]

Most of codegen is already FP64-ready. There are a few edge-cases that I ran into, many of which can apply even to non-fp64-enabled programs (although the double-wide registers are not very common without fp64). I've yet to give this a full piglit run, but wanted to send these out in case someone wanted to comment. They do not depend on the preliminary core fp64 work. Ilia Mirkin (5):