Displaying 2 results from an estimated 2 matches for "getpartialregupdateclearance".
2013 Mar 25
2
[LLVMdev] About the partial update clearence / dependency breaking mechanism
Hello,
I am currently looking into the advantages of using the
partial update clearance / dependency breaking mechanism
for some ARM cores.
It seems that the ARM specific code for this will always
return a clearance of 0 for VLD1LNd32 because of the following
code in getPartialRegUpdateClearance:
> if (UseOp != -1 && MI->getOperand(UseOp).readsReg())
> return 0;
so essentially VLD1LNd32 (and potentially other instruction)
will never be affected by this. Was this intended or is there
a bug here?
I'm confused why the dependency breaking code is correct.
Why would...
2013 Mar 25
0
[LLVMdev] About the partial update clearence / dependency breaking mechanism
...;
> I am currently looking into the advantages of using the
> partial update clearance / dependency breaking mechanism
> for some ARM cores.
>
> It seems that the ARM specific code for this will always
> return a clearance of 0 for VLD1LNd32 because of the following
> code in getPartialRegUpdateClearance:
>
>> if (UseOp != -1 && MI->getOperand(UseOp).readsReg())
>> return 0;
>
> so essentially VLD1LNd32 (and potentially other instruction)
> will never be affected by this. Was this intended or is there
> a bug here?
>
> I'm confused why the depend...