search for: getord

...Both operands are required, even if "failure" is the natural pair of "success" Semantically, I would like to enforce the constraints in the standards: + failure <= success + failure != Release + failure != AcquireRelease. Before the DAG, I suggest completely removing getOrdering from CmpXchgInst, in favour of getSuccessOrdering and getFailureOrdering to avoid errors. In the DAG, getOrdering would still exist and return the success ordering, which I believe would make existing targets conservatively correct. AtomicSDNode would add getFailureOrdering, used only by ATOMI...

Hi everyone I've got a problem regarding the arima() and the ar() function for autoregressive series. I would simply like to combine them. To better understand my question, I first show you how I'm using these two functions individually (see file in the attachement). 1) apply(TSX,2, function(x) ar(na.omit(x),method="mle")$order # this function finds the optimal

...the resulting node has the earlier source order, and the debug location should match. > > That way, CSE simply looks like the last definition of a value has been removed. Debug location and source order of the first definition should be preserved. hmm… I agree with Jakob. See SelectionDAG::GetOrdering() - Devang

...getType() == > + cast<LoadInst>(J)->getPointerOperand()->getType()&& > + cast<LoadInst>(I)->isVolatile() == > + cast<LoadInst>(J)->isVolatile()&& > + cast<LoadInst>(I)->getOrdering() == > + cast<LoadInst>(J)->getOrdering()&& > + cast<LoadInst>(I)->getSynchScope() == > + cast<LoadInst>(J)->getSynchScope() > + ) { > + isCompat = true; > +...

...t; + cast<LoadInst>(J)->getPointerOperand()->getType()&& > > + cast<LoadInst>(I)->isVolatile() == > > + cast<LoadInst>(J)->isVolatile()&& > > + cast<LoadInst>(I)->getOrdering() == > > + cast<LoadInst>(J)->getOrdering()&& > > + cast<LoadInst>(I)->getSynchScope() == > > + cast<LoadInst>(J)->getSynchScope() > > + ) { > > + isC...

On Sep 14, 2011, at 7:37 AM, Richard Osborne wrote: > Is there a view on which of the following approaches is better in > general when two nodes with debug locations are merged because of CSE > (either in the MachineCSE pass or because of the CSEMap in the > SelectionDAG): > > 1) Use the DebugLoc of either of the pair of nodes (chosen arbitrarily). > 2) Throw away the

Tobias, et al., Attached is the my autovectorization pass. I've fixed a bug that appears when using -bb-vectorize-aligned-only, fixed some 80-col violations, etc., and at least on x86_64, all test cases pass except for a few; and all of these failures look like instruction-selection bugs. For example: MultiSource/Applications/ClamAV - fails to compile shared_sha256.c with an error: error in

Tobias, I've attached the latest version of my autovectorization patch. I was able to add support for using the ScalarEvolution analysis for load/store pairing (thanks for your help!). This led to a modest performance increase and a modest compile-time increase. This version also has a cutoff as you suggested (although the default value is set high (4000 instructions between pairs) because

..._list_del Cyclomatic Complexity 1 include/linux/list.h:list_empty Cyclomatic Complexity 1 arch/x86/include/asm/current.h:get_current Cyclomatic Complexity 3 include/linux/string.h:memset Cyclomatic Complexity 5 include/linux/string.h:memcpy Cyclomatic Complexity 1 include/asm-generic/getorder.h:__get_order Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:arch_atomic_dec_and_test Cyclomatic Complexity 1 include/asm-generic/atomic-instrumented.h:atomic_dec_and_test Cyclomatic Complexity 1 include/linux/err.h:PTR_ERR Cyclomatic Complexity 1 include/linux/thread_info.h:se...

On 13/09/11 17:40, Devang Patel wrote: > On Sep 13, 2011, at 4:01 AM, Kyriakos Georgiou wrote: >> I've been investigating a case with the XCore target (which doesn't use >> FastISel) where the DWARF line number emitted at -O0 results in the xgdb >> visiting source lines in an unexpected order. I've tracked down the >> problem to the handling of DebugLocs in

On 11/19/2014 4:05 AM, Chandler Carruth wrote: > > On Fri, Nov 14, 2014 at 1:09 PM, Sahasrabuddhe, Sameer > <sameer.sahasrabuddhe at amd.com <mailto:sameer.sahasrabuddhe at amd.com>> > wrote: > > 1. Update the synchronization scope field in atomic instructions > from a > single bit to a wider field, say 32-bit unsigned integer. > > > I

...erOperand()->getType() == > + cast<LoadInst>(J)->getPointerOperand()->getType()&& > + cast<LoadInst>(I)->isVolatile() == > + cast<LoadInst>(J)->isVolatile()&& > + cast<LoadInst>(I)->getOrdering() == > + cast<LoadInst>(J)->getOrdering()&& > + cast<LoadInst>(I)->getSynchScope() == > + cast<LoadInst>(J)->getSynchScope() > + ) { > + IsCompat = true; > + } > + }...

...ype() == > > + cast<LoadInst>(J)->getPointerOperand()->getType()&& > > + cast<LoadInst>(I)->isVolatile() == > > + cast<LoadInst>(J)->isVolatile()&& > > + cast<LoadInst>(I)->getOrdering() == > > + cast<LoadInst>(J)->getOrdering()&& > > + cast<LoadInst>(I)->getSynchScope() == > > + cast<LoadInst>(J)->getSynchScope() > > + ) { > > + IsCompat = true; > &...

On Mon, 2011-11-21 at 21:22 -0600, Hal Finkel wrote: > On Mon, 2011-11-21 at 11:55 -0600, Hal Finkel wrote: > > Tobias, > > > > I've attached an updated patch. It contains a few bug fixes and many > > (refactoring and coding-convention) changes inspired by your comments. > > > > I'm currently trying to fix the bug responsible for causing a compile

...ass (ex: element unordered-atomic memcpy is recognized as a MemCpyInst, MemTransferInst, and a MemIntrinsic), and add a query method like ‘isUnorderedAtomic’ that will tell you whether the underlying intrinsic is one of the element atomic variants. Alternatively, the method could be a more generic ‘getOrdering()’ that would return an AtomicOrdering; though a memory intrinsic that is required to be implemented with ordered-atomic instructions strikes me as unlikely to ever be desired. There is precedent for encoding the intrinsic property as a query method both within the current memory intrinsic h...

...ype() == > > + cast<LoadInst>(J)->getPointerOperand()->getType()&& > > + cast<LoadInst>(I)->isVolatile() == > > + cast<LoadInst>(J)->isVolatile()&& > > + cast<LoadInst>(I)->getOrdering() == > > + cast<LoadInst>(J)->getOrdering()&& > > + cast<LoadInst>(I)->getSynchScope() == > > + cast<LoadInst>(J)->getSynchScope() > > + ) { > > + IsCompat = true; > &...

On Mon, 2011-11-21 at 11:55 -0600, Hal Finkel wrote: > Tobias, > > I've attached an updated patch. It contains a few bug fixes and many > (refactoring and coding-convention) changes inspired by your comments. > > I'm currently trying to fix the bug responsible for causing a compile > failure when compiling >

Hi: This series tries to fix various issues of vhost: - Patch 1 adds a missing write barrier between used idx updating and logging. - Patch 2-3 brings back the protection of device IOTLB through vq mutex, this fixes possible use after free in device IOTLB entries. - Patch 4 fixes the diry page logging when device IOTLB is enabled. We should done through GPA instead of GIOVA, this was done

Hi: This series tries to fix various issues of vhost: - Patch 1 adds a missing write barrier between used idx updating and logging. - Patch 2-3 brings back the protection of device IOTLB through vq mutex, this fixes possible use after free in device IOTLB entries. - Patch 4 fixes the diry page logging when device IOTLB is enabled. We should done through GPA instead of GIOVA, this was done

A call to drm_simple_encoder_init() initializes an encoder without further functionality. It only provides the destroy callback to cleanup the encoder's state. Only few drivers implement more sophisticated encoders than that. Most drivers implement such a simple encoder and can use drm_simple_encoder_init() instead. The patchset converts drivers where the encoder's instance is embedded in