search for: getopcod

...it was a MemSDNode, then isa<MemSDNode> evaluates to true if you are in one of the following cases: static bool classof(const SDNode *N) { // For some targets, we lower some target intrinsics to a MemIntrinsicNode // with either an intrinsic or a target opcode. return N->getOpcode() == ISD::LOAD || N->getOpcode() == ISD::STORE || N->getOpcode() == ISD::PREFETCH || N->getOpcode() == ISD::ATOMIC_CMP_SWAP || N->getOpcode() == ISD::ATOMIC_SWAP || N->get...

...target. I set ISD::ADD to be custom expanded (setOperationAction(ISD::ADD, MVT::i64, Custom)) and the same for ISD::SUB. I then added the following code to my target to do the expansion: ExpandADDSUB(SDNode *N, SelectionDAG &DAG) { assert(N->getValueType(0) == MVT::i64 && (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && "Unknown operand to lower!"); // Extract components SDOperand LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), DAG.getConstant(0, MVT::i32)); SDOperand LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,...

> -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Duncan Sands > Sent: Thursday, March 31, 2011 7:43 PM > To: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] Assert in VerifySDNode > > Hi Micah, > > > assert(!isa<MemSDNode>(N) && "Bad MemSDNode!"); > > you

...ion 2118) +++ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (.../branches/llvm-spu) (revision 2118) @@ -2683,10 +2683,24 @@ case ISD::ROTR: Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS - - assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && - "Cannot handle this yet!"); Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); + switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { + default: + assert(0 && "ROTL/ROTR legali...

...rstand correctly, Operator is basically a trivial temporary object that holds some common functionality for both Instruction and ConstantExpr. It looks to me like Operator is doing something illegal though. For example, in this member function of class Operator (in include/llvm/Operator.h): /// getOpcode - Return the opcode for this Instruction or ConstantExpr. /// unsigned getOpcode() const { if (const Instruction *I = dyn_cast<Instruction>(this)) return I->getOpcode(); return cast<ConstantExpr>(this)->getOpcode(); } In this function, the `this` pointer is n...

My target doesn't support 64 bit arithmetic, so I'd like to supply definitions for adde/addc. The problem is I can't seem to figure out the magic. Here's an example of what I need to generate: # two i64s in r5/r6 and r7/r8 # result in r1/r2, carry in r3 # adde add r2, r6, r8 cmpltu r3, r2, r6 # compute carry # addc add r1, r5, r7 add r1, zero, r3 Is this

...y a trivial temporary > object that holds some common functionality for both Instruction and > ConstantExpr. > > It looks to me like Operator is doing something illegal though. For > example, in this member function of class Operator (in > include/llvm/Operator.h): > > /// getOpcode - Return the opcode for this Instruction or ConstantExpr. > /// > unsigned getOpcode() const { > if (const Instruction *I = dyn_cast<Instruction>(this)) > return I->getOpcode(); > return cast<ConstantExpr>(this)->getOpcode(); > } > > In...

Hi, >> DAGCombiner::visitBRCOND() has code: >> >> SDValue N1 = N->getOperand(1); >> SDValue N2 = N->getOperand(2); >> >> ... >> >> SDNode *Trunc = 0; >> if (N1.getOpcode() == ISD::TRUNCATE&& N1.hasOneUse()) { >> // Look past truncate. >> Trunc = N1.getNode(); >> N1 = N1.getOperand(0); >> } >> >> which just drops the truncate away. this looks wrong. According to the documentation of BRCOND, // B...

Hi All, In SVN head, MipsISelDAGToDAG.cpp has the following optimization: // Operand is a result from an ADD. if (Addr.getOpcode() == ISD::ADD) { // When loading from constant pools, load the lower address part in // the instruction itself. Example, instead of: // lui $2, %hi($CPI1_0) // addiu $2, $2, %lo($CPI1_0) // lwc1 $f0, 0($2) // Generate: // lui $2, %hi($CPI1_0) // lwc1 $f...

...E = prior(DAG.allnodes_end()); I != next(E); ++I) { + bool HasVectorValue = false; + for (SDNode::value_iterator J = I->value_begin(); J != I->value_end(); ++J) + HasVectorValue |= J->isVector(); + if (!HasVectorValue) continue; + SDNode* Result = I; + switch (I->getOpcode()) { + default: + assert(I->getOpcode() > ISD::BUILTIN_OP_END && "Unexpected node!"); + break; + case ISD::UNDEF: + case ISD::FORMAL_ARGUMENTS: + case ISD::CALL: + case ISD::MERGE_VALUES: + case ISD::RET: + case ISD::VAARG: + case ISD::Regi...

...patternDC::runOnFunction(Function &F) { ... ifChecker* CC=new ifChecker(); if ( CC->operEquiv(ifsInstrArray[i], ifsInstrArray[j]) ) ... and bool ifChecker::operEquiv(Instruction *I1, Instruction *I2){ if (I1!=NULL && I2!=NULL) //if (I1->getOpcode() != I2->getOpcode()) return false; return true; } When I decomment the line from operEquiv, I have the segfault. See gdb output: 0xb7fd6ff0 <_ZN12_GLOBAL__N_19ifChecker9operEquivEPN4llvm11InstructionES3_+16>: movzbl 0x4(%edx),%edx What is the problem? Thank you !...

...g point select_cc's into fsel instruction when @@ -3980,59 +3919,203 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) { const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); - assert((MI->getOpcode() == PPC::SELECT_CC_I4 || - MI->getOpcode() == PPC::SELECT_CC_I8 || - MI->getOpcode() == PPC::SELECT_CC_F4 || - MI->getOpcode() == PPC::SELECT_CC_F8 || - MI->getOpcode() == PPC::SELECT_CC_VRRC) && - "Unexpected instr type to inse...

ok.. you are right. I had not inserted the AllocaInst in the function. Thanks a lot for solving my problem yet again :) --- On Mon, 11/17/08, Eli Friedman <eli.friedman at gmail.com> wrote: > From: Eli Friedman <eli.friedman at gmail.com> > Subject: Re: Assertion `castIsValid(getOpcode(), S, Ty) && "Illegal BitCast"' faile > To: bhavi63 at yahoo.com > Date: Monday, November 17, 2008, 6:04 AM > On Sun, Nov 16, 2008 at 9:53 PM, bhavani krishnan > <bhavi63 at yahoo.com> wrote: > > Ah! I get it now.. thanks a lot Eli! > > > >...

...brcond, jumping on condition based on the lowest bit. This routine then goes to SelectionDAG:Combine() which runs DAGCombiner::visitBRCOND(). DAGCombiner::visitBRCOND() has code: SDValue N1 = N->getOperand(1); SDValue N2 = N->getOperand(2); ... SDNode *Trunc = 0; if (N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) { // Look past truncate. Trunc = N1.getNode(); N1 = N1.getOperand(0); } which just drops the truncate away.. then there is another optimization afterwards.. // Transform br(xor(x, y)) -> br(x != y) // Transform br(xor(xor(x...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...g point select_cc's into fsel instruction when @@ -3981,59 +3920,198 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) { const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); - assert((MI->getOpcode() == PPC::SELECT_CC_I4 || - MI->getOpcode() == PPC::SELECT_CC_I8 || - MI->getOpcode() == PPC::SELECT_CC_F4 || - MI->getOpcode() == PPC::SELECT_CC_F8 || - MI->getOpcode() == PPC::SELECT_CC_VRRC) && - "Unexpected instr type to inse...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

...anywhere in the codebase that actually uses the ConvertAction to determine how conversion functions are lowered? In SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) ... case ISD::SINT_TO_FP: case ISD::UINT_TO_FP: case ISD::EXTRACT_VECTOR_ELT: Action = TLI.getOperationAction(Node->getOpcode(), Node->getOperand(0).getValueType()); This seems incorrect as SINT_TO_FP should be querying the convert action, and not the Operation action. i.e. it should be: case ISD::SINT_TO_FP: case ISD::UINT_TO_FP: case ISD::FP_TO_SINT: case ISD::FP_TO_UINT...

...bject that holds some common functionality for both Instruction and >> ConstantExpr. >> >> It looks to me like Operator is doing something illegal though. For >> example, in this member function of class Operator (in >> include/llvm/Operator.h): >> >> /// getOpcode - Return the opcode for this Instruction or ConstantExpr. >> /// >> unsigned getOpcode() const { >> if (const Instruction *I = dyn_cast<Instruction>(this)) >> return I->getOpcode(); >> return cast<ConstantExpr>(this)->getOpcode(); &...

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const