Displaying 20 results from an estimated 45 matches for "getnumvalues".
2008 Aug 18
5
[LLVMdev] Type Legalizer - Load handling problem
...ll LOAD:i8 with an i16 operand be lowered in type legalizer? (i16
type is not legal for our target)
Following assertion in function ExpandIntegerOperand (file
LegalizeIntegerTypes.cpp) is not allowing us to change LOAD node.
assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() ==
1 && "Invalid operand expansion");
LOAD node has two values but the assertion checks N->getNumValues() == 1
which is not letting us change load operation.
Also in the first check of the insertion, 0th value type (MVT::Other
(chain) for load) of the node N is being...
2008 Aug 19
2
[LLVMdev] Type Legalizer - Load handling problem
On Mon, 2008-08-18 at 08:50 -0700, Eli Friedman wrote:
> On Mon, Aug 18, 2008 at 6:31 AM, <Sachin.Punyani at microchip.com> wrote:
> > assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
> > "Invalid operand expansion");
> >
> > LOAD node has two values but the assertion checks N->getNumValues() == 1
> > which is not letting us change load operation.
>
Besides the assert, the call to
ReplaceValueWith(SDValue(N, 0), Res);...
2009 Apr 08
4
[LLVMdev] What is the state of LLVM's ARM backend
...eturn-values-cross-block-with-invoke.ll | llc
llc: /usr/src/openembedded/overo/tmp/work/armv7a-angstrom-linux-gnueabi/llvm2.6-2.6-r0/llvm-2.6/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1579: llvm::SDValue<unnamed>::SelectionDAGLegalize::LegalizeOp(llvm::SDValue): Assertion `(Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() || (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 && Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) == MVT::Flag)) && "Lowering call/formal_arguments produced unexpected # results!&q...
2008 Aug 18
0
[LLVMdev] Type Legalizer - Load handling problem
On Mon, Aug 18, 2008 at 6:31 AM, <Sachin.Punyani at microchip.com> wrote:
> assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
> "Invalid operand expansion");
>
> LOAD node has two values but the assertion checks N->getNumValues() == 1
> which is not letting us change load operation.
I don't really know the right answer here, but custom-legalizing to a
backend-specific load o...
2008 Aug 19
0
[LLVMdev] Type Legalizer - Load handling problem
...8:07 AM, sanjiv gupta
<sanjiv.gupta at microchip.com> wrote:
> On Mon, 2008-08-18 at 08:50 -0700, Eli Friedman wrote:
>> On Mon, Aug 18, 2008 at 6:31 AM, <Sachin.Punyani at microchip.com> wrote:
>> > assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
>> > "Invalid operand expansion");
>> >
>> > LOAD node has two values but the assertion checks N->getNumValues() == 1
>> > which is not letting us change load operation.
>>
> Besides the assert, the call to
> ReplaceVa...
2006 Nov 15
2
[LLVMdev] LowerCALL (TargetLowering)
...ike intrinsics, except
that these are custom to my target.) I do not need to implement any call
sequences, stack frames etc.
I get the following assertion failure:
llc: LegalizeDAG.cpp:834: llvm::SDOperand <unnamed>::SelectionDAGLegalize::LegalizeOp(llvm::SDOperand): Assertion `Tmp3.Val->getNumValues() == Result.Val->getNumValues() && "Lowering call/formal_arguments produced unexpected # results!"' failed.
This is what my LowerCALL looks like:
SDOperand MCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
SDOperand Chain = Op.getOperand(0);
b...
2009 Apr 01
0
[LLVMdev] What is the state of LLVM's ARM backend
LLVM ARM v6 backend is in fairly good shape. Even the JIT passes
nearly the entire llvm test suite. There are some known missing bits:
1. Exception handling
2. Atomic
Not sure:
3. Debugging support (should be trivial to hook up if it's not done)
Also the thumb backend is not awesome. Its performance is not great.
Evan
On Apr 1, 2009, at 6:34 AM, Robert Schuster wrote:
> Hi,
> the
2009 Apr 01
4
[LLVMdev] What is the state of LLVM's ARM backend
Hi,
the ARM backend lacks some stuff like support for atomic intrinsics. I
learned the hard way (crash). Lately I was told that the ARM backend of
LLVM is generally in its early stages of development.
I would like to know more about this. Which stuff is missing, known to
be unstable and the like.
Thanks in advance for taking the time.
Regards
Robert
-------------- next part --------------
A
2006 Nov 15
0
[LLVMdev] LowerCALL (TargetLowering)
...to my target.) I do not need to implement any
> call
> sequences, stack frames etc.
>
> I get the following assertion failure:
>
> llc: LegalizeDAG.cpp:834: llvm::SDOperand
> <unnamed>::SelectionDAGLegalize::LegalizeOp(llvm::SDOperand):
> Assertion `Tmp3.Val->getNumValues() == Result.Val->getNumValues()
> && "Lowering call/formal_arguments produced unexpected # results!"'
> failed.
>
> This is what my LowerCALL looks like:
>
> SDOperand MCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG
> &DAG) {
> S...
2008 Aug 29
0
[LLVMdev] Type Legalizer - Load handling problem
...arts of
the code generator assume that the type of a pointer is legal.
> Following assertion in function ExpandIntegerOperand (file
> LegalizeIntegerTypes.cpp) is not allowing us to change LOAD node.
>
>
>
> assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() ==
> 1 && "Invalid operand expansion");
>
>
>
> LOAD node has two values but the assertion checks N->getNumValues() == 1
> which is not letting us change load operation.
Yup, in this case you need to return an SDValue with null Val field,
and take care...
2008 Oct 20
2
[LLVMdev] TableGen Hacking Help
...perty(Pattern, SDNPHasChain, CGP);
to call PatternHasProperty instead. This does cause tblgen to emit
getTargetNode / ReplaceUses instead of SelectNodeTo but ReplaceUses doesn't
know how to handle a complex pattern like this. It complains about having
two many operands:
assert(From->getNumValues() == 1 && FromN.ResNo == 0 &&
"Cannot replace with this method!");
From->getNumValues() > 1 so this croaks.
So I'm going to need a little help. Either SelectionDAG::ReplaceAllUsesWith
needs to be able to handle more complex things or tblgen needs to...
2008 Aug 19
1
[LLVMdev] Type Legalizer - Load handling problem
...gupta
> <sanjiv.gupta at microchip.com> wrote:
>> On Mon, 2008-08-18 at 08:50 -0700, Eli Friedman wrote:
>>> On Mon, Aug 18, 2008 at 6:31 AM, <Sachin.Punyani at microchip.com> wrote:
>>> > assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
>>> > "Invalid operand expansion");
>>> >
>>> > LOAD node has two values but the assertion checks N->getNumValues() == 1
>>> > which is not letting us change load operation.
>>>
>> Besides the assert, the...
2008 Aug 29
2
[LLVMdev] Type Legalizer - Load handling problem
> > LOAD node has two values but the assertion checks N->getNumValues() == 1
> > which is not letting us change load operation.
>
> Yup, in this case you need to return an SDValue with null Val field,
> and take care of replacing values yourself.
That said, it looks like it is done this way because no-one needed
anything more. It could easily be ch...
2010 Sep 25
2
[LLVMdev] custom lowering with multiple results
Here's a concrete example of what I'm having problems with:
trying to use LowerOperation to replace one node with two nodes.
Imagine I have a new instruction "read_world" that sets the status flags
according to some kind of global state. In order to generate this instruction I
have a built-in function with the prototype "int __builtin_read_world(void)".
I also have a
2006 Nov 15
1
[LLVMdev] LowerCALL (TargetLowering)
...nt any
> > call
> > sequences, stack frames etc.
> >
> > I get the following assertion failure:
> >
> > llc: LegalizeDAG.cpp:834: llvm::SDOperand
> > <unnamed>::SelectionDAGLegalize::LegalizeOp(llvm::SDOperand):
> > Assertion `Tmp3.Val->getNumValues() == Result.Val->getNumValues()
> > && "Lowering call/formal_arguments produced unexpected # results!"'
> > failed.
> >
> > This is what my LowerCALL looks like:
> >
> > SDOperand MCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG...
2007 Sep 28
0
[LLVMdev] Lowering operations to 8-bit!
On Sep 28, 2007, at 11:36 AM, <Alireza.Moshtaghi at microchip.com>
<Alireza.Moshtaghi at microchip.com> wrote:
> I moved my code to 2.1 but still the same.
> If I make ADD i16 legal, then it goes through, but it has problem
> expanding it to i8.
> Should I go ahead and customize it and do the same for all
> instructions?
> Or there is a more general thing that I
2007 Sep 28
2
[LLVMdev] Lowering operations to 8-bit!
I moved my code to 2.1 but still the same.
If I make ADD i16 legal, then it goes through, but it has problem
expanding it to i8.
Should I go ahead and customize it and do the same for all instructions?
Or there is a more general thing that I can do?
A.
-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
On Behalf Of Chris Lattner
Sent:
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...if (&*I != Result) {
+ Changed = true;
+ DAG.ReplaceAllUsesWith(I, Result);
+ }
+ }
+
+ // Remove dead nodes now.
+ DAG.RemoveDeadNodes();
+
+ return Changed;
+}
+
+SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
+ MVT VT = Op.getValueType();
+ assert(Op.getNode()->getNumValues() == 1 &&
+ "Can't promote a vector with multiple results!");
+ MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
+ DebugLoc dl = Op.getDebugLoc();
+ SmallVector<SDValue, 4> Operands(Op.getNumOperands());
+
+ for (unsigned j = 0; j != Op.getNumOperands();...
2007 Sep 28
2
[LLVMdev] Lowering operations to 8-bit!
...es;
SDOperand Root = Op.getOperand(0);
// Return the new list of results.
std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
Op.Val->value_end());
const Function* Fn = DAG.getMachineFunction().getFunction();
std::cout<<Op.Val->getNumValues();
std::cout<<"----------------- "<<__FUNCTION__<<" handling
FORMAL_ARGUMENTS of"<<Fn->getName()<<std::endl;std::cout.flush();
for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e;
++ArgNo) {
MVT::ValueType ObjectVT =...
2008 Dec 09
1
[LLVMdev] [PATH] Add sub.ovf/mul.ovf intrinsics
...erflow.ll to:
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 0, i32 0)
causes the following exception when running the codegen tests:
llc: DAGCombiner.cpp:646:
void<unnamed>::DAGCombiner::Run(llvm::CombineLevel): Assertion
`N->getValueType(0) == RV.getValueType() && N->getNumValues() == 1 &&
"Type mismatch"' failed.
0 llc 0x00000000010601ef
1 llc 0x00000000010604ec
2 libc.so.6 0x00007f58a754df60
3 libc.so.6 0x00007f58a754ded5 gsignal + 53
4 libc.so.6 0x00007f58a754f3f3 abort + 387
5 libc.so.6 0x00007f58a7546dc9 __assert_fail + 233...