Displaying 5 results from an estimated 5 matches for "getnumdefs".
2012 Dec 26
0
[LLVMdev] Getting MCInst "ins" and "outs"
The MCInstrDesc has a method getNumDefs() which tells you how many 'out registers' that MCInst has. The 'out' registers are always at the beginning of the list. You can also use getNumOperands().
Not sure if this is what you are looking for.
-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmd...
2012 Dec 23
5
[LLVMdev] Getting MCInst "ins" and "outs"
Hi all.
I'm looking for some way to do code analysis with LLVM. Can someone please give me a hint, if it is possible to query an MCInst for what are input operands and what are output operands?
Small example.
Consider we have an instruction:
str r1, [sp, #8]
Being mapped into MCInst instance it has the following operands:
<MCOperand Reg:61> <-- maps to reg r1
2012 Dec 26
1
[LLVMdev] Getting MCInst "ins" and "outs"
Hi,
Am Mittwoch, 26. Dezember 2012, 15:20:27 schrieb Manny Ko:
> The MCInstrDesc has a method getNumDefs() which tells you how many 'out
> registers' that MCInst has. The 'out' registers are always at the beginning
> of the list. You can also use getNumOperands().
I've run into the problem, that this doesn't work for instructions which have
variadic arguments like Push...
2012 Sep 25
2
[LLVMdev] Distinguish variadic register defines/uses in MCInstrDesc?
...uctions writing to the program counter) and to differentiate between
register definitions and uses to track all instructions the branch depends on.
This works well for most cases, except if there are Thumb pop instructions
involved.
Pop has a variable number of output registers, so MCInstrDesc::getNumDefs
returns zero and, as far as I can see, in the tablegen files 'variable_ops' is
always in the 'ins' list and MCInstrDesc only provides isVariadic();
My current workaround is to assume that all variadic arguments of instructions
that have zero register definitions but are marked a...
2017 Feb 11
2
Specify special cases of delay slots in the back end
Hello.
Hal, the problem I have is that it doesn't advance at the next available instruction
- it always gets the same store. This might be because I did not specify in a file like
[Target]Schedule.td the functional units, processor and instruction itineraries.
Regarding the Stalls argument to my method
[Target]DispatchGroupSBHazardRecognizer::getHazardType() I always get the