Displaying 6 results from an estimated 6 matches for "getnumberofregist".
2013 Aug 23
1
[LLVMdev] how do I disable vectorization passes for a target by default?
Hi
I would like to disable vectorization on the XCore target by default.
I assume I need to push_back -fno-vectorize in clang/lib/driver/Tools.cpp for Triple::xcore.
Should I also disable the pass in llvm explicitly?
I tried setting getNumberOfRegisters in XCoreTTI::TargetTransformInfo viz:
unsigned getNumberOfRegisters(bool Vector) const {
if (Vector) {
return 0;
}
return 12;
}
But this made no difference (I need to double check).
What is the correct way to disable vectorization passes?
Robert
-------------- next pa...
2018 Jul 24
2
KNL Vectorization with larger vector width
...r instructions.
How to do this?
What adjustments are needed?
Please help
I m trying this but unable to solve.
Thank You
On Tue, Jul 24, 2018 at 4:44 PM, hameeza ahmed <hahmed2305 at gmail.com> wrote:
> Hello,
> Do i need to change following function;
>
> unsigned X86TTIImpl::getNumberOfRegisters(bool Vector) {
> if (Vector && !ST->hasSSE1())
> return 0;
>
> if (ST->is64Bit()) {
> if (Vector && ST->hasAVX512())
> return 32;
> return 16;
> }
> return 8;
> }
>
> to
>
> if (ST->is2048Bit()) {
>...
2018 Jul 24
2
KNL Vectorization with larger vector width
Thank You.
Right now to see the effect i did following changes;
unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) {
if (Vector) {
if (ST->hasAVX512())
return 65536;
here i changed 512 to 65536. Then in loopvectorize.cpp i did following;
assert(MaxVectorSize <= 2048 && "Did not expect to pack so many elements"
" into
2013 Jan 09
0
[LLVMdev] ARM vectorizer cost model
...ext switches. Do you mean the cost of moving GPR to NEON ? Its a good point. We need to increase the cost of insert/extract vector. It should be easy to model and we have all of the hooks already.
We can use the Subtarget when we implement the hooks. This is an example from the ARMTTI
unsigned getNumberOfRegisters(bool Vector) const {
if (Vector) {
if (ST->hasNEON())
return 16;
return 0;
}
if (ST->isThumb1Only())
return 8;
return 16;
}
unsigned getMaximumUnrollFactor() const {
// These are out of order CPUs:
if (ST->isCortexA15() || ST-...
2013 Jan 09
2
[LLVMdev] ARM vectorizer cost model
Hi Nadav,
I'm interested in knowing how you'll work up the ARM cost model and how
easy it'd be to split the work.
As far as I can see, LoopVectorizationCostModel is the class that does all
the work, with assistance from the target transform info.
Do you think that updating ARMTTI would be the best course of action now,
and inspect the differences in the CostModel later?
I also
2016 Sep 01
2
enabling interleaved access loop vectorization
So turns out it is a full reproducer after all (choosing to vectorize on AVX), good.
> The details are in PR29025.
Interesting. (So we should carefully insert unconditional branches inside shuffle sequences, eh? ;-)
> But if we modify the program by adding "*out++ = 0" right after "*out++ = q;" (thus eliminating the pesky <12 x i8>), we get:
Indeed such