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..."Expanded integer type size not a power of two!"); DebugLoc dl = N->getDebugLoc(); // Get the incoming operand to be shifted. SDValue InL, InH; GetExpandedInteger(N->getOperand(0), InL, InH); SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy); SDValue Amt2 = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt); SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy), Amt, NVBitsNode, ISD::SETULT); SDValue Lo1, Hi1, Lo2, Hi2; switch (N->getOpcode()) { default: llvm_unreachable("Unknown shift"); case ISD::SHL:...

On Mon, Nov 30, 2009 at 7:22 PM, Javier Martinez <javier at jmartinez.org> wrote: > Hello, > > I'm working in adding support for 64-bit integers to my target. I'm using > LLVM to decompose the 64-bit integer operations by using 32-bit registers > wherever possible and emulating support where not. When looking at the bit > shift decomposition I saw what seems to be a

...ret void } In the DAG matching code generated from the .td file there is : if (N1.getOpcode() == ISD::ADD && N1.hasOneUse()) { SDValue N10 = N1.getOperand(0); if (N10.getOpcode() == ISD::LOAD && N10.hasOneUse() && IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) && (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) { ... NEED TO MATCH ABOVE TO GENERATE MEMORY TO MEMORY PATTERN } When debugged we get: N10.hasOneUse() = 1 IsLegalAndProfitableToFold(N10.getNo...

On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more

On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant

...urn SDValue(); + assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!"); + + // Make a 64-bit buffer, and use it to build an FILD. + SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); + SDValue WordOff = DAG.getConstant(4, getPointerTy()); + SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, + getPointerTy(), StackSlot, WordOff); + SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op, StackSlot, NULL, 0); + SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), + OffsetSlot, NULL, 0);...

...de to my target to do the expansion: ExpandADDSUB(SDNode *N, SelectionDAG &DAG) { assert(N->getValueType(0) == MVT::i64 && (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && "Unknown operand to lower!"); // Extract components SDOperand LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), DAG.getConstant(0, MVT::i32)); SDOperand LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), DAG.getConstant(1, MVT::i32)); SDOperand RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(1), DAG.getConstant(...

My target doesn't support 64 bit arithmetic, so I'd like to supply definitions for adde/addc. The problem is I can't seem to figure out the magic. Here's an example of what I need to generate: # two i64s in r5/r6 and r7/r8 # result in r1/r2, carry in r3 # adde add r2, r6, r8 cmpltu r3, r2, r6 # compute carry # addc add r1, r5, r7 add r1, zero, r3 Is this

The LegalizeDAG.cpp file has this code in SelectionDAGLegalize::PromoteNode: case ISD::BSWAP: { unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1); Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); Results.push_back(Tmp1); break; } Notice the first DAG.getNode() call. It's...

...e() == ISD::Constant) { + uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); + uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); if ((LShVal + RShVal) != OpSizeInBits) return 0; SDOperand Rot; if (HasROTL) - Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0), - LHSShift.getOperand(1)); + Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); else - Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0), - RHSShift.getOperand(1)); + Rot = DAG.g...

Hi All, In XCore backend, I saw “ …... EVT VT = Op.getValueType(); SDValue Data = DAG.getNode(XCoreISD::CRC8, DL, DAG.getVTList(VT, VT), Op.getOperand(1), Op.getOperand(2) , Op.getOperand(3)); SDValue Crc(Data.getNode(), 1); SDValue Results[] = { Crc, Data }; return DAG.getMergeValues(Results, 2, DL); “ which is used to lower an instruction that retur...

...t;> >> SDValue N1 = N->getOperand(1); >> SDValue N2 = N->getOperand(2); >> >> ... >> >> SDNode *Trunc = 0; >> if (N1.getOpcode() == ISD::TRUNCATE&& N1.hasOneUse()) { >> // Look past truncate. >> Trunc = N1.getNode(); >> N1 = N1.getOperand(0); >> } >> >> which just drops the truncate away. this looks wrong. According to the documentation of BRCOND, // BRCOND - Conditional branch. The first operand is the chain, the // second is the condition, the third is the blo...

...h" @@ -5666,7 +5667,7 @@ void SDNode::dump() const { dump(0); } void SDNode::dump(const SelectionDAG *G) const { - print(errs(), G); + print(dbgs(), G); } void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const { @@ -5834,12 +5835,12 @@ if (N->getOperand(i).getNode()->hasOneUse()) DumpNodes(N->getOperand(i).getNode(), indent+2, G); else - errs() << "\n" << std::string(indent+2, ' ') - << (void*)N->getOperand(i).getNode() << ": <multiple use>"; + dbgs() <&l...

Hello LLVM, A recent commit creates the isIntDivCheap() target query. http://reviews.llvm.org/D12082 The current approach has a couple shortcomings. First, when targets decide divide is cheap, the DAGCombiner ignores obvious power-of-2 optimizations. In the targets I know, shifts are cheaper than divides in both speed and size. The target cannot see the value in the isIntDivCheap() call, so

...pp (working copy) @@ -3415,12 +3415,16 @@ // (*ext (rotr x, (sub 32, y))) SDValue LArgExtOp0 = LHSShiftArg.getOperand(0); EVT LArgVT = LArgExtOp0.getValueType(); - if (LArgVT.getSizeInBits() == SUBC->getAPIntValue()) { - SDValue V = - DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, LArgVT, - LArgExtOp0, HasROTL ? LHSShiftAmt : RHSShiftAmt); - return DAG.getNode(LHSShiftArg.getOpcode(), DL, VT, V).getNode(); - } + bool HasROTRWithLArg = TLI.isOperationLegalOrCustom(ISD::ROTR, LArgVT); +...

...::FEXP2: + case ISD::FCEIL: + case ISD::FTRUNC: + case ISD::FRINT: + case ISD::FNEARBYINT: + case ISD::FFLOOR: + switch (TLI.getOperationAction(I->getOpcode(), I->getValueType(0))) { + case TargetLowering::Promote: + Result = PromoteVectorOp(SDValue(Result, 0)).getNode(); + break; + case TargetLowering::Legal: break; + case TargetLowering::Custom: { + SDValue Tmp1 = TLI.LowerOperation(SDValue(Result, 0), DAG); + if (Tmp1.getNode()) { + // FIXME: Should the returned value be recursively checked? + Result = Tmp1.get...

...d still shows up in trunk. case ISD::SUB: { EVT VT = Node->getValueType(0); assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && TLI.isOperationLegalOrCustom(ISD::XOR, VT) && "Don't know how to expand this subtraction!"); Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT)); Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); break; } Th...

...har *)malloc(2048); strcpy(exprStrChar, "test... ..."); SDValue extSym = CurDAG->getTargetExternalSymbol( exprStrChar, MVT::i64); SDNode *extSymNode = extSym.getNode(); std::vector<SDValue> opsRes; opsRes.push_back(SDValue(vloadSpecial, 0)); opsRes.push_back(extSym); // Creating an SDNode MDNode<null> (MetaData) with a ch out port SDNode *mdNodeSDNode = CurDAG->getNode(ISD::MDNODE_SDNODE, DL,...

On Dec 22, 2009, at 2:38 PMPST, Bill Wendling wrote: > The LegalizeDAG.cpp file has this code in > SelectionDAGLegalize::PromoteNode: > > case ISD::BSWAP: { > unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); > Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1); > Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); > Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, > DAG.getConstant(DiffBits, > TLI.getShiftAmountTy())); > Results.push_back(Tmp1); > break; > } > > Notic...

...ne() which runs DAGCombiner::visitBRCOND(). DAGCombiner::visitBRCOND() has code: SDValue N1 = N->getOperand(1); SDValue N2 = N->getOperand(2); ... SDNode *Trunc = 0; if (N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) { // Look past truncate. Trunc = N1.getNode(); N1 = N1.getOperand(0); } which just drops the truncate away.. then there is another optimization afterwards.. // Transform br(xor(x, y)) -> br(x != y) // Transform br(xor(xor(x,y), 1)) -> br (x == y) if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { SDNod...