Displaying 2 results from an estimated 2 matches for "getmipsregisternumbering".
2011 Oct 10
2
[LLVMdev] Adding fixups and relocations late in code generation
...#########################
unsigned MipsMCCodeEmitter::
getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const {
const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isReg()) {
unsigned Reg = MO.getReg();
unsigned RegNo = getMipsRegisterNumbering(Reg);
return RegNo;
} else if (MO.isImm()) {
return static_cast<unsigned>(MO.getImm());
} else if (MO.isFPImm()) {
return static_cast<unsigned>(APFloat(MO.getFPImm())
.bitcastToAPInt().getHiBits(32).getLimitedValue());
} else if (MO.isExpr()) {
const...
2011 Oct 10
0
[LLVMdev] Adding fixups and relocations late in code generation
...CCodeEmitter::
> getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
> SmallVectorImpl<MCFixup> &Fixups) const {
>
> const MCOperand &MO = MI.getOperand(OpNo);
>
> if (MO.isReg()) {
> unsigned Reg = MO.getReg();
>
> unsigned RegNo = getMipsRegisterNumbering(Reg);
> return RegNo;
>
> } else if (MO.isImm()) {
> return static_cast<unsigned>(MO.getImm());
> } else if (MO.isFPImm()) {
> return static_cast<unsigned>(APFloat(MO.getFPImm())
> .bitcastToAPInt().getHiBits(32).getLimitedValue());
> } els...