search for: getminimalphysregclass

On 05/14/2012 02:17 PM, Jakob Stoklund Olesen wrote: > On May 14, 2012, at 1:02 PM, reed kotler wrote: > >> Does anyone understand the purpose of : >> >> TargetRegisterInfo::getMinimalPhysRegClass ??? > Barely. > >> Why is there the presumption to use the minimal subclass? > The function can be traced back to a time when men were men and registers belonged to ONE register class. That concept doesn't make sense any longer, as LLVM supports and aggressively uses overlapping...

On May 14, 2012, at 1:02 PM, reed kotler wrote: > Does anyone understand the purpose of : > > TargetRegisterInfo::getMinimalPhysRegClass ??? Barely. > Why is there the presumption to use the minimal subclass? The function can be traced back to a time when men were men and registers belonged to ONE register class. That concept doesn't make sense any longer, as LLVM supports and aggressively uses overlapping register classes...

Does anyone understand the purpose of : TargetRegisterInfo::getMinimalPhysRegClass ??? Why is there the presumption to use the minimal subclass? For Mips, it would work for me if we changed this to a virtual function and then I could override this to have it chose the proper register class based on the processor. I want to introduct a different register class for MIPS 16 but...

On May 14, 2012, at 2:28 PM, reed kotler wrote: > I'm not using getMinimalPhysRegClass. Some target independent code is using it. Probably PEI. > It makes trouble for us and I would like to submit a patch to make it a virtual function so that I can override it and make it meaningful for Mips, as long as this method still exists. > > I want to add another register class fo...

Reed, On May 14, 2012, at 3:45 PM, reed kotler <rkotler at mips.com> wrote: > On 05/14/2012 02:42 PM, Jakob Stoklund Olesen wrote: >> On May 14, 2012, at 2:28 PM, reed kotler wrote: >> >>> I'm not using getMinimalPhysRegClass. Some target independent code is using it. >> Probably PEI. >> >>> It makes trouble for us and I would like to submit a patch to make it a virtual function so that I can override it and make it meaningful for Mips, as long as this method still exists. >>> >>&gt...

On 05/14/2012 02:42 PM, Jakob Stoklund Olesen wrote: > On May 14, 2012, at 2:28 PM, reed kotler wrote: > >> I'm not using getMinimalPhysRegClass. Some target independent code is using it. > Probably PEI. > >> It makes trouble for us and I would like to submit a patch to make it a virtual function so that I can override it and make it meaningful for Mips, as long as this method still exists. >> >> I want to add anothe...

Does anyone understand the purpose of this target inpdendent function? By adding a new register class that is for MIPS16 but not even referencing it, the compiler breaks because of this code. def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add // Return Values and Arguments V0, V1, A0, A1, A2, A3, // Callee save S0, S1 )>; I'm trying to understand how the

...pushing an interference of current SUnit. 2. having no more SUnits in the AvailableQueue 3. The only interference being the SUnit that just failed due to a Call Resource. 4. An attempt to duplicate this node which has the 'Call Resource' as a physical register. Thus the call to getMinimalPhysRegClass() asserts - Call Resource is not in a class! ..../lib/CodeGen/TargetRegisterInfo.cpp:120: const llvm::TargetRegisterClass* llvm::TargetRegisterInfo::getMinimalPhysRegClass(unsigned int, llvm::EVT) const: Assertion `BestRC && "Couldn't find the register class"' failed. Th...

...pushing an interference of current SUnit. 2. having no more SUnits in the AvailableQueue 3. The only interference being the SUnit that just failed due to a Call Resource. 4. An attempt to duplicate this node which has the 'Call Resource' as a physical register. Thus the call to getMinimalPhysRegClass() asserts - Call Resource is not in a class! ..../lib/CodeGen/TargetRegisterInfo.cpp:120: const llvm::TargetRegisterClass* llvm::TargetRegisterInfo::getMinimalPhysRegClass(unsigned int, llvm::EVT) const: Assertion `BestRC && "Couldn't find the register class"' failed. Th...

...pushing an interference of current SUnit. 2. having no more SUnits in the AvailableQueue 3. The only interference being the SUnit that just failed due to a Call Resource. 4. An attempt to duplicate this node which has the 'Call Resource' as a physical register. Thus the call to getMinimalPhysRegClass() asserts - Call Resource is not in a class! ..../lib/CodeGen/TargetRegisterInfo.cpp:120: const llvm::TargetRegisterClass* llvm::TargetRegisterInfo::getMinimalPhysRegClass(unsigned int, llvm::EVT) const: Assertion `BestRC && "Couldn't find the register class"' failed. Th...

...pushing an interference of current SUnit. 2. having no more SUnits in the AvailableQueue 3. The only interference being the SUnit that just failed due to a Call Resource. 4. An attempt to duplicate this node which has the 'Call Resource' as a physical register. Thus the call to getMinimalPhysRegClass() asserts - Call Resource is not in a class! ..../lib/CodeGen/TargetRegisterInfo.cpp:120: const llvm::TargetRegisterClass* llvm::TargetRegisterInfo::getMinimalPhysRegClass(unsigned int, llvm::EVT) const: Assertion `BestRC && "Couldn't find the register class"' failed. Th...

...with B in a machine instruction? My concern is that A may be in a restricted register class of which B is not a member. An example is trying to replace the x86 CL register in a shift operation. It seems like the only way to get a register class for a physical register is via TargetRegisterInfo::getMinimalPhysRegClass but that is far too conservative in general. Is there any way, given an instruction and a register operand, to find out which exact register class models the semantics/restrictions of that operand position in the instruction? -David

...oReg() can be eliminated - it will only ever be called for physical registers. This means that the implementation can be simpler, and sometimes better code can be generated. A register may be allocated to a more conveniently than the register class specifies. It also means that most of the annoying getMinimalPhysRegClass() calls go away. 4. The COPY instruction does not impose register class constraints on its operands, native copies do. This is important when we implement live interval splitting in the register allocator. After splitting an interval the register class can be recomputed. Without the copy constrain...

...I am not sure I follow this. Why would the regclass arguments be eliminated? > means that the implementation can be simpler, and sometimes better code can be generated. A register may be allocated to a more conveniently than the register class specifies. It also means that most of the annoying getMinimalPhysRegClass() calls go away. True. > > 4. The COPY instruction does not impose register class constraints on its operands, native copies do. This is important when we implement live interval splitting in the register allocator. After splitting an interval the register class can be recomputed. Without...

Hi, When using Wine to run Windows ARM64 executables on Linux, there's one major ABI incompatibility between the two; Windows treats the x18 register as the reserved platform register, while it is free to be clobbered anywhere in code on Linux. The Wine code sets up this register before passing control over to the Windows executable code, but whenever the Windows code calls a function

...Machine::~LLVMTargetMachine()in libLLVMCodeGen.a(LLVMTargetMachine.cpp.o) llvm::LLVMTargetMachine::~LLVMTargetMachine()in libLLVMCodeGen.a(LLVMTargetMachine.cpp.o) llvm::LLVMTargetMachine::~LLVMTargetMachine()in libLLVMCodeGen.a(LLVMTargetMachine.cpp.o) "llvm::TargetRegisterInfo::getMinimalPhysRegClass(unsigned int, llvm::EVT) const", referenced from: llvm::PEI::calculateCalleeSavedRegisters(llvm::MachineFunction&) in libLLVMCodeGen.a(PrologEpilogInserter.cpp.o) llvm::PEI::insertCSRSpillsAndRestores(llvm::MachineFunction&) in libLLVMCodeGen.a(PrologEpilogInserter.cp...

...->isDeallocRet(MI)) { >> + if (DepReg == QRI->getFrameRegister() || >> + DepReg == QRI->getStackRegister()) >> + return true; >> + } >> + >> + // Check if this is a predicate dependence >> + const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg); >> + if (RC == Hexagon::PredRegsRegisterClass) { >> + return true; >> + } >> + >> + // >> + // Lastly check for an operand used in an indirect call >> + // If we had an attribute for checking if an instruction is an indirect call, >>...