search for: getmergevalu

...I saw “ …... EVT VT = Op.getValueType(); SDValue Data = DAG.getNode(XCoreISD::CRC8, DL, DAG.getVTList(VT, VT), Op.getOperand(1), Op.getOperand(2) , Op.getOperand(3)); SDValue Crc(Data.getNode(), 1); SDValue Results[] = { Crc, Data }; return DAG.getMergeValues(Results, 2, DL); “ which is used to lower an instruction that returns two values. I am trying to something like this: ” ……. SDValue z = DAG.getNode(my_ISD::test_op, DL, VT, Op.getOperand(0); SDValue w = DAG.getConstant(1, MVT::i32); SDValue DataZ = DAG.getNode(ISD::BUILDER_VECTOR, DL, MVT::v4i...

...etMemOperand(); cast<MachineSDNode>(LDW)->setMemRefs(MemOp, MemOp + 1); // Reshuffle LDW's results so that the first two match LOAD's result // type SDValue Unpack[] = { SDValue(LDW, 0), SDValue(LDW, 2), SDValue(LDW, 1) }; SDNode* NN = CurDAG->getMergeValues(Unpack, SDLoc(N)).getNode(); ReplaceUses(N, NN); CurDAG->RemoveDeadNode(N); With this code, I get correct-looking machine instructions, but the node order is all botched up. For example, given this input: SelectionDAG has 8 nodes: t0: ch = EntryToken t2: i16,ch = Cop...

...achineSDNode>(LDW)->setMemRefs(MemOp, MemOp + 1); > > // Reshuffle LDW's results so that the first two match LOAD's > result > // type > SDValue Unpack[] = { SDValue(LDW, 0), SDValue(LDW, 2), > SDValue(LDW, 1) }; > SDNode* NN = CurDAG->getMergeValues(Unpack, SDLoc(N)).getNode(); Calling getMergeValues in ISelDAGToDAG is a bad idea; there aren't supposed to be any MERGE_VALUES nodes at that point in the pipeline. You can call ReplaceUses with SDValues rather than SDNodes. -Eli -- Employee of Qualcomm Innovation Center, Inc. Qualcomm...

...erand(0); Ops[numNodes++] = Op.getOperand((inChain) ? 2 : 1); Ops[numNodes++] = DAG.getConstant(1, MVT::i32); Ops[numNodes++] = DAG.getTargetConstant(0, MVT::i32); Op = DAG.getNode(IntNo, dl, EVT::EVT(MVT::i32), Ops, numNodes); if (outChain) { SDValue mv[2] = {Op, chain}; Op = DAG.getMergeValues(mv, 2, dl); } return Op; } I'm guessing I am not handling the chain correctly, but I'm not sure what I am doing wrong. Can someone point me to an example of matching an intrinsic to a machine instruction with no return value? Thanks, Micah -------------- next part -------------- An...

Tks Cameron, I did some study on it. Now I am having the same problem as mentioned in this thread;"http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-January/057654.html” , > Looking at the X86 back-end code, it looks like there do exist > multi-output instructions, but they all use physical (implicit) registers > for the second destination, not arbitrary register types. And if I

...Op.getOperand((inChain) ? 2 : 1); > Ops[numNodes++] = DAG.getConstant(1, MVT::i32); > Ops[numNodes++] = DAG.getTargetConstant(0, MVT::i32); > Op = DAG.getNode(IntNo, dl, EVT::EVT(MVT::i32), Ops, numNodes); > if (outChain) { > SDValue mv[2] = {Op, chain}; > Op = DAG.getMergeValues(mv, 2, dl); > } > return Op; > } > > I’m guessing I am not handling the chain correctly, but I’m not sure what I am doing wrong. Can someone point me to an example of matching an intrinsic to a machine instruction with no return value? > > Thanks, > Micah > ____...

...ffectively look like this: // Reg is RAX or EAX, based on the subtarget Chain = DAG.getNode(X86ISD::SEG_ALLOCA, dl, NodeTys, Chain, Flag); Flag = Chain.getValue(1); Chain = DAG.getCopyFromReg(Chain, dl, Reg, SPTy).getValue(1); SDValue Ops1[2] = { Chain.getValue(0), Chain }; return DAG.getMergeValues(Ops1, 2, dl); Firstly, I would also like some feedback on this implementation in general. Secondly, the problem I'm facing: in the final assembly generated, the move instruction to RAX, in (c) is absent. I suspected this has something to do with the liveness analysis pass. With -debug-only=...

...1); > > Ops[numNodes++] = DAG.getConstant(1, MVT::i32); > > Ops[numNodes++] = DAG.getTargetConstant(0, MVT::i32); > > Op = DAG.getNode(IntNo, dl, EVT::EVT(MVT::i32), Ops, numNodes); > > if (outChain) { > > SDValue mv[2] = {Op, chain}; > > Op = DAG.getMergeValues(mv, 2, dl); > > } > > return Op; > > } > > > > I'm guessing I am not handling the chain correctly, but I'm not sure > what I am doing wrong. Can someone point me to an example of matching > an intrinsic to a machine instruction with no return value?...

...". - SDOperand Ops2[] = { - Chain, // Chain - NewVal, // Value - Ptr, // Ptr - Label, // Label - }; - SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops2, 4); - SDOperand OutOps[] = { Load, Store }; - return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), OutOps, 2); + return DAG.getNode(PPCISD::ATOMIC_LOAD_ADD, VTs, Ops, 3); } SDOperand PPCTargetLowering::LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG) { @@ -2762,39 +2743,14 @@ SDOperand NewVal = Op.getOperand(2); SDOperand OldVal = Op.getOpera...

...eg is RAX or EAX, based on the subtarget > Chain = DAG.getNode(X86ISD::SEG_ALLOCA, dl, NodeTys, Chain, Flag); > Flag = Chain.getValue(1); > Chain = DAG.getCopyFromReg(Chain, dl, Reg, SPTy).getValue(1); > > SDValue Ops1[2] = { Chain.getValue(0), Chain }; > return DAG.getMergeValues(Ops1, 2, dl); > > Firstly, I would also like some feedback on this implementation in general. > > Secondly, the problem I'm facing: in the final assembly generated, the > move instruction to RAX, in (c) is absent. I suspected this has > something to do with the liveness anal...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...". - SDOperand Ops2[] = { - Chain, // Chain - NewVal, // Value - Ptr, // Ptr - Label, // Label - }; - SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops2, 4); - SDOperand OutOps[] = { Load, Store }; - return DAG.getMergeValues(OutOps, 2); + return DAG.getNode(PPCISD::ATOMIC_LOAD_ADD, VTs, Ops, 3); } SDOperand PPCTargetLowering::LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG) { @@ -2762,39 +2743,14 @@ SDOperand NewVal = Op.getOperand(2); SDOperand OldVal = Op.getOperand(3); - // Issue a "lo...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:

You need to insert new basic blocks and update CFG to accomplish this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See

...". - SDOperand Ops2[] = { - Chain, // Chain - NewVal, // Value - Ptr, // Ptr - Label, // Label - }; - SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops2, 4); - SDOperand OutOps[] = { Load, Store }; - return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), OutOps, 2); + return DAG.getNode(PPCISD::ATOMIC_LOAD_ADD, VTs, Ops, 3); } SDOperand PPCTargetLowering::LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG) { @@ -2762,39 +2743,14 @@ SDOperand NewVal = Op.getOperand(2); SDOperand OldVal = Op.getOpera...

Would it be acceptable to change MachineInstr::getRegInfo from private to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter? Cheers, Gary Evan Cheng wrote: > Look for createVirtualRegister. These are examples in > PPCISelLowering.cpp. > > Evan > On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > > > Hi Evan, > > > > Evan Cheng wrote:

Chris Lattner wrote: > On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > > $label), > > "cmpw $rA, $rB\n\tbne- La${label}_exit", > > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > > $label)]>; > > } > > > > ...and

...". - SDOperand Ops2[] = { - Chain, // Chain - NewVal, // Value - Ptr, // Ptr - Label, // Label - }; - SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops2, 4); - SDOperand OutOps[] = { Load, Store }; - return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), OutOps, 2); + return DAG.getNode(PPCISD::ATOMIC_LOAD_ADD, VTs, Ops, 3); } SDOperand PPCTargetLowering::LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG) { @@ -2762,39 +2743,14 @@ SDOperand NewVal = Op.getOperand(2); SDOperand OldVal = Op.getOpera...