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On Nov 10, 2008, at 1:20 PM, Daniel M Gessel wrote: > I've been running into two issues with load/store handling: > > (1) is that tablegen doesn't seem to handle the two predicates that > get attached to my instructions. The first is the predicate in > TargetSelectionDAG.td, identifying a load node as, say, extloadi8. The > second is my identification of the load as

I've been running into two issues with load/store handling: (1) is that tablegen doesn't seem to handle the two predicates that get attached to my instructions. The first is the predicate in TargetSelectionDAG.td, identifying a load node as, say, extloadi8. The second is my identification of the load as having a particular address space (need different instructions for different

...// Perform the nonatomic load. auto *Node = cast<AtomicSDNode>(AtomicOp.getNode()); SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(AtomicOp), AtomicOp.getValueType(), Node->getChain(), Node->getBasePtr(), Node->getMemoryVT(), Node->getMemOperand()); auto Restore = DAG.getCopyToReg(DAG.getEntryNode(), DL, AVR::SREG, Save); return Load; I can’t figure out how I can glue all these nodes together and return the nonatomic load. How can I do this? Cheers, Dylan ​ -------------- next part -------------- An HTML...

...else bestOffset = (uint64_t)offset * (width/8); bestMask = Mask.lshr(offset * (width/8) * 8); - bestWidth = width; + EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), width); + if (isNarrowingProfitable(Lod->getMemoryVT(), NewVT)) + bestWidth = width; break; } newMask = newMask << width;

...ce, please add a doxygen comment. +++ lib/Target/X86/X86ISelDAGToDAG.cpp (working copy) @@ -1548,6 +1548,107 @@ + case ISD::STORE: { + // Handle unaligned non-temporal stores. + StoreSDNode *ST = cast<StoreSDNode>(Node); + DebugLoc dl = Node->getDebugLoc(); + EVT VT = ST->getMemoryVT(); + if (VT.isVector() && + VT.isFloatingPoint() && + VT.getSizeInBits() == 128 && + ST->getAlignment() < 16) { + // Unaligned stores This is completely unrelated to your patch. +++ lib/VMCore/PassManager.cpp (working copy) #include &q...

...how to enter this section of code: // If this is an unaligned load and the target doesn't support it, // expand it. if (!TLI.allowsUnalignedMemoryAccesses()) { unsigned ABIAlignment = TLI.getTargetData()-> getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); if (LD->getAlignment() < ABIAlignment){ Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, TLI); Tmp1 = Result.getOperand(0); Tmp2 = Res...

On Friday 12 March 2010 08:13:05 Kalle Raiskila wrote: > David Greene wrote: > > Here's a rework using PassManager as Chris suggested. Comments? > > Tried this second patch with the svn version 97812 (the one the patch is > made against), but it doesn't compile: > "llvm/include/llvm/Pass.h:127: Error: expected unqualified-id before "&" >

David Greene wrote: > Here's a rework using PassManager as Chris suggested. Comments? Tried this second patch with the svn version 97812 (the one the patch is made against), but it doesn't compile: "llvm/include/llvm/Pass.h:127: Error: expected unqualified-id before "&" token" Seems raw_ostream is forward declared but not defined (adding a missing #include

...+++ lib/Target/X86/X86ISelDAGToDAG.cpp (working copy) > @@ -1548,6 +1548,107 @@ > > + case ISD::STORE: { > + // Handle unaligned non-temporal stores. > + StoreSDNode *ST = cast<StoreSDNode>(Node); > + DebugLoc dl = Node->getDebugLoc(); > + EVT VT = ST->getMemoryVT(); > + if (VT.isVector() && > + VT.isFloatingPoint() && > + VT.getSizeInBits() == 128 && > + ST->getAlignment() < 16) { > + // Unaligned stores > > This is completely unrelated to your patch. Erk. I thought I got rid...

On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more

On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant

...= DAG.getNode(ISD::RET, dl, MVT::Other, - &NewValues[0], NewValues.size()); + Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); break; } } @@ -2618,8 +2201,7 @@ } } - switch (getTypeAction(ST->getMemoryVT())) { - case Legal: { + { Tmp3 = LegalizeOp(ST->getValue()); Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, ST->getOffset()); @@ -2653,111 +2235,8 @@ } break; } - case Promote: -...

...t; } > > +SDValue SITargetLowering::LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const > +{ > + SDLoc DL(Op); > + > + AtomicSDNode *Swap = cast<AtomicSDNode>(Op); > + assert(Swap && Swap->isCompareAndSwap()); > + > + EVT MemVT = Swap->getMemoryVT(); > + EVT ValVT = EVT::getVectorVT(*DAG.getContext(), MemVT, 2); > + SDValue Cmp = Op.getOperand(2); > + SDValue New = Op.getOperand(3); > + > + // "src comes from the first data-vgpr, cmp from the second." > + SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, DL, ValVT...

Hi Tom, Matt, I'm working on a project that needs few coherent atomic operations (HSA mode: load, store, compare-and-swap) for std::atomic_uint in HCC. the attached patch implements atomic compare and swap for SI+ (untested). I tried to stay within what was available, but there are few issues that I was unsure how to address: 1.) it currently uses v2i32 for both input and output. This

...AtomicSDNode *N) { SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) { SDValue Op2 = GetPromotedInteger(N->getOperand(2)); SDValue Op3 = GetPromotedInteger(N->getOperand(3)); - SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N), - N->getMemoryVT(), N->getChain(), N->getBasePtr(), - Op2, Op3, N->getMemOperand(), N->getOrdering(), - N->getSynchScope()); + SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(), + N->...