search for: getmemoryoperandno

...operands held in order by the MachineInstr, from an offset onwards - Base, Scale, Index, Displacement, Segment. The former, if I understand it correctly, is used to hold a relationship back to IR load/store instructions. Is it possible to have a X86 MachineInstr with a memory operand (i.e. X86II::getMemoryOperandNo >=0), that has no MachineMemOperand? What about the reverse? Thanks, Mircea. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180308/e27ca0e4/attachment.html>

...write code like: > const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); > const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); for both MachineInstrs and MCInsts. > > Is it possible to have a X86 MachineInstr with a memory operand (i.e. X86II::getMemoryOperandNo >=0), that has no MachineMemOperand? What about the reverse? > * Attaching a MachineMemOperand to an instruction that doesn’t reference any memory: From what I tried, the instruction has to be marked as “mayLoad / mayStore” (you can see them in X86InstrInfo.td) in order to pass the verifie...

Thanks for the details! How should we think of the case where an instruction has memory operands (in the sense that X86II::getMemoryOperandNo >=0), but doesn't have MachineMemOperands? I'm seeing an example in the case of __builtin_prefetch (lowered via SelectionDAG::getMemIntrinsicNode, which produces a MachineMemOperand) vs __builtin_ia32_gatherpfdpd, lowered through getPrefetchNode in X86ISelLowering.cpp. The latter doesn&...

My team interested in doing some post-RA optimizations on X86 instructions, which would require identifying memory reference instructions. In the X86 back end instructions, memory addresses consist of a set of five operands. The offset to the start of the five operands depends on the format of the instruction. For instance, the instructions ADC32rm, ADD32rm, AND32rm, ANDN32rm, CMOVA32rm,