search for: getmemoperand

...LD->getBasePtr(), LD->getChain()); // Honestly, I have no idea what this does, but other memory // accessing instructions have something similar... MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); MemOp[0] = cast<MemSDNode>(N)->getMemOperand(); cast<MachineSDNode>(LDW)->setMemRefs(MemOp, MemOp + 1); // Reshuffle LDW's results so that the first two match LOAD's result // type SDValue Unpack[] = { SDValue(LDW, 0), SDValue(LDW, 2), SDValue(LDW, 1) }; SDNode* NN = CurDAG->getMergeValu...

...load. auto *Node = cast<AtomicSDNode>(AtomicOp.getNode()); SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(AtomicOp), AtomicOp.getValueType(), Node->getChain(), Node->getBasePtr(), Node->getMemoryVT(), Node->getMemOperand()); auto Restore = DAG.getCopyToReg(DAG.getEntryNode(), DL, AVR::SREG, Save); return Load; I can’t figure out how I can glue all these nodes together and return the nonatomic load. How can I do this? Cheers, Dylan ​ -------------- next part -------------- An HTML attachment was scrubbed......

...asePtr(), LD->getChain()); > > // Honestly, I have no idea what this does, but other memory > // accessing instructions have something similar... > MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); > MemOp[0] = cast<MemSDNode>(N)->getMemOperand(); > cast<MachineSDNode>(LDW)->setMemRefs(MemOp, MemOp + 1); > > // Reshuffle LDW's results so that the first two match LOAD's > result > // type > SDValue Unpack[] = { SDValue(LDW, 0), SDValue(LDW, 2), > SDValue(LDW, 1) }; >...

...gt;getBasePtr(), Val}; > + ArrayRef<EVT> VTs = { MVT::v2i32, MVT::Other }; > + SDVTList VTList = { VTs.data(), VTs.size() }; > + > + SDValue CmpSwap = DAG.getMemIntrinsicNode(AMDGPUISD::CMP_SWAP, DL, VTList, > + Ops, MemVT, Swap->getMemOperand()); > + // TODO: What about ordering? synchscope? > + > + // Extract returned old value > + SDValue Zero = DAG.getConstant(0, DL, MVT::i32); > + SDValue Old = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, > + CmpSwap.getValue(0), Zero); > +...

Hi Tom, Matt, I'm working on a project that needs few coherent atomic operations (HSA mode: load, store, compare-and-swap) for std::atomic_uint in HCC. the attached patch implements atomic compare and swap for SI+ (untested). I tried to stay within what was available, but there are few issues that I was unsure how to address: 1.) it currently uses v2i32 for both input and output. This

.../CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -2878,6 +2878,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) { Node->getOperand(1), Zero, Zero, cast<AtomicSDNode>(Node)->getMemOperand(), cast<AtomicSDNode>(Node)->getOrdering(), + cast<AtomicSDNode>(Node)->getOrdering(), cast<AtomicSDNode>(Node)->getSynchScope()); Results.push_back(Swap.getValue(0));...