Displaying 10 results from an estimated 10 matches for "getlocreg".
2013 Feb 02
0
[LLVMdev] Moving return value registers from MRI to return instructions
...Context());
CCInfo.AnalyzeReturn(Outs, RetCC_X86);
- // Add the regs to the liveout set for the function.
- MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
- for (unsigned i = 0; i != RVLocs.size(); ++i)
- if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
- MRI.addLiveOut(RVLocs[i].getLocReg());
-
SDValue Flag;
-
SmallVector<SDValue, 6> RetOps;
RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
// Operand #1 = Bytes To Pop
@@ -1666,6 +1659,7 @@ X86TargetLowering::LowerReturn(SDValue Chain,
Chain = DAG.ge...
2016 Sep 23
2
Misuse of MRI.getRegClass in multiple target's FastIsel code
...register class enum value and get
the register class object for it. It doesn't convert a register to a class.
In fact there's not always a single or canonical class for a given register.
What is the right way to do this?
unsigned SrcReg = Reg + VA.getValNo();
unsigned DestReg = VA.getLocReg();
// Avoid a cross-class copy. This is very unlikely.
if (!MRI.getRegClass(SrcReg)->contains(DestReg))
return false;
~Craig
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2012 Oct 26
1
[LLVMdev] Properly handling mem-loc arguments when prologue adjusts FP.
...it wouldn't be able to guess
that. But here I'm just conjecturing - may not be relevant!
Thanks,
Stephen
[1]: LowerCall
...
// Arguments that can be passed in a register must be kept in the
// RegsToPass vector.
if (VA.isRegLoc()) {
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
} else {
// Sanity check.
assert(VA.isMemLoc());
// Get the stack pointer if needed.
if (StackPtr.getNode() == 0) {
StackPtr = DAG.getCopyFromReg(Chain, dl, ARC::SP, getPointerTy());
}
SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerT...
2016 Feb 01
2
TableGen customized node with mayStore attribute is deleted if there is no use
...egister class. I
implement it in LowerFormalArguments() like this:
....
for (auto &VA : ArgLocs) {
if (VA.isRegLoc()) {
// Arguments passed in registers
EVT RegVT = VA.getLocVT();
VReg = RegInfo.createVirtualRegister(&FOO::BRegsRegClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg);
SDValue ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
SDValue ArgIn_copy = DAG.getNode(FOOISD::MOVE_FLAG , dl, MVT::i32,
Chain, ArgIn); // this node is added in order to move the value from BRegs
class to ARegs class and I want it be kept even it is not used later on...
2015 Nov 25
2
need help for customized backend LowerFormalArguments
...ontext());
CCInfo.AnalyzeFormalArguments(Ins, CC_FOO);
for (auto &VA : ArgLocs) {
if (VA.isRegLoc()) {
// Arguments passed in registers
EVT RegVT = VA.getLocVT();
const unsigned VReg =
RegInfo.createVirtualRegister(&FOO::PRegsRegClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg);
SDValue ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
InVals.push_back(ArgIn);
continue;
}
// assume the parameter registers are enough, no need to store in frame
right now
}
return Chain;
}
In the above function, CC_FOO is defined in CallingConv.td a...
2007 Sep 11
0
[LLVMdev] RFC: Tail call optimization X86
...better to check
whether the last call is a tail call on the fly as you are processing
the return node.
8.
-
- SDOperand Chain = Op.getOperand(0);
- SDOperand Flag;
-
- // Copy the result values into the output registers.
- if (RVLocs.size() != 1 || !RVLocs[0].isRegLoc() ||
- RVLocs[0].getLocReg() != X86::ST0) {
- for (unsigned i = 0; i != RVLocs.size(); ++i) {
- CCValAssign &VA = RVLocs[i];
- assert(VA.isRegLoc() && "Can only return in registers!");
- Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand
(i*2+1),
-...
2007 Sep 06
2
[LLVMdev] RFC: Tail call optimization X86
Hi Evan,
first off thanks to you and Chris for taking time.
On 6 Sep 2007, at 00:57, Evan Cheng wrote:
> We'd like to see tail call optimization to be similar to the target
> independent lowering of ISD::CALL nodes. These are auto-generated
> from ???CallingConv.td files. Some target specific details such as
> function address register (ECX in your example) should be coded in
2012 Oct 06
2
[LLVMdev] Pairing Registers on a Target Similar to Mips?
...Arg, DAG.getConstant(0, MVT::i32));
SDValue Hi = DAG.getNode(MIPSISD::ExtractElementF64, dl, MVT::i32,
Arg, DAG.getConstant(1, MVT::i32));
if (!Subtarget->isLittle())
std::swap(Lo, Hi);
unsigned LocRegLo = VA.getLocReg();
unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
I added this SDValue:
SDValue Num = DAG.getNode(MIPSISD::CopyF64,dl,MVT::i32, Arg);
But I need to creat...
2007 Sep 11
2
[LLVMdev] RFC: Tail call optimization X86
...on the fly as you are processing
> the return node.
Will do so.
> 8.
> -
> - SDOperand Chain = Op.getOperand(0);
> - SDOperand Flag;
> -
> - // Copy the result values into the output registers.
> - if (RVLocs.size() != 1 || !RVLocs[0].isRegLoc() ||
> - RVLocs[0].getLocReg() != X86::ST0) {
> - for (unsigned i = 0; i != RVLocs.size(); ++i) {
> - CCValAssign &VA = RVLocs[i];
> - assert(VA.isRegLoc() && "Can only return in registers!");
> - Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand
> (i*2+1),
>...
2012 Oct 09
0
[LLVMdev] Pairing Registers on a Target Similar to Mips?
...i32));
> SDValue Hi = DAG.getNode(MIPSISD::ExtractElementF64, dl,
> MVT::i32,
> Arg, DAG.getConstant(1, MVT::i32));
>
> if (!Subtarget->isLittle())
> std::swap(Lo, Hi);
>
> unsigned LocRegLo = VA.getLocReg();
> unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
>
> RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
> RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
>
> I added this SDValue:
> SDValue Num = DAG.getNode(MIPSISD::CopyF64,dl,MVT...