search for: getlatencystallcycl

...' and then the pattern repeats itself. All of these are loads. > Even without that limit, stalls take precedence over load clustering. So when you run out of load resources (15?) the scheduler should choose something else. > Is this the code that checks for stalls? if (tryLess(Zone.getLatencyStallCycles(TryCand.SU), Zone.getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall)) It is disabled if (!SU->isUnbuffered) > > I have a feeling there is something wrong with my machine model in the > > R600 backend, but I've experimented with a few variations of it and h...

Hi, I have a program with over 100 loads (each with a 10 cycle latency) at the beginning of the program, and I can't figure out how to get the machine scheduler to intermix ALU instructions with the loads to effectively hide the latency. It seems the issue is with load clustering. I restrict load clustering to 4 at a time, but when I look at the debug output, the loads are always being

Hi Andy, Thanks for the explanations. Yes AMDGPU is in-order and has MicroOpBufferSize = 1. Re "issue limited" and instruction groups: could it make sense to disable the generic scheduler's detection of issue limitation on in-order CPUs, or on CPUs that don't define instruction groups, or some similar condition? Something like: --- a/lib/CodeGen/MachineScheduler.cpp +++