search for: getinterv

...is of some interest. The crash happens in LiveIntervalsAnalysis, inside the spilling function. From what I observe, I'd say it is related to rematerializable intervals. The assertion says: /opt/llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h:142: llvm::LiveInterval& llvm::LiveIntervals::getInterval(unsigned int): Assertion `I != r2iMap_.end() && "Interval does not exist for register"' failed. I attach the BC file generated by bugpoint, so that you can reproduce it. The command-line I use is: llc --regalloc=linearscan --march=xcore -f bugpoint-reduced-simplified.bc...

...SVI->second.DefByOrigPHI = true; >> SVI->second.AllDefsAreReloads = false; >> propagateSiblingValue(SVI); >> continue; >> } >> // check if the valno is actually an orig PHI, but is not OrigVNI >> else { >> LiveInterval &OrigLI = LIS.getInterval(Original); >> VNInfo *OrigVNI_curr = OrigLI.getVNInfoAt(VNI->def); >> if (OrigVNI_curr->def == VNI->def) >> assert(0 && "OrigLI contained VNI which was a PHI, but not OrigVNI!"); >> } >> >> , but the assert never triggered a...

...ash happens in LiveIntervalsAnalysis, inside the spilling > function. From what I observe, I'd say it is related to > rematerializable intervals. > > The assertion says: > /opt/llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h:142: > llvm::LiveInterval& llvm::LiveIntervals::getInterval(unsigned int): > Assertion `I != r2iMap_.end() && "Interval does not exist for > register"' failed. > > I attach the BC file generated by bugpoint, so that you can reproduce it. > > The command-line I use is: > llc --regalloc=linearscan --march=xcore -f...

...valsAnalysis, inside the spilling >> function. From what I observe, I'd say it is related to >> rematerializable intervals. >> >> The assertion says: >> /opt/llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h:142: >> llvm::LiveInterval& llvm::LiveIntervals::getInterval(unsigned int): >> Assertion `I != r2iMap_.end() && "Interval does not exist for >> register"' failed. >> >> I attach the BC file generated by bugpoint, so that you can >> reproduce it. >> >> The command-line I use is: >> llc...

...Slot == VirtRegMap::NO_STACK_SLOT) { > StackSlot = VRM.assignVirt2StackSlot(Original); > StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original)); > StackInt->getNextValue(SlotIndex(), LSS.getVNInfoAllocator()); > } else > StackInt = &LSS.getInterval(StackSlot); > > if (Original != Edit->getReg()) > VRM.assignVirt2StackSlot(Edit->getReg(), StackSlot); > > assert(StackInt->getNumValNums() == 1 && "Bad stack interval values"); > for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) >...

Hi, Can anyone help me with the stack slot coloring optimization? This corresponding file is /lib/codegen/stackslotcoloring.cpp. It is said this optimization was for stack slot overlay for frame size reduction, after register allocation phase. And this transformation pass relies on the LiveStack analysis pass. How, when checking the source code, it seems the LiveStack analysis has not been

...r() && mop.getReg() && MRegisterInfo::isVirtualRegister(mop.getReg())) { // replace register with representative register unsigned reg = rep(mop.getReg()); mii->SetMachineOperandReg(i, reg); LiveInterval &RegInt = getInterval(reg); RegInt.weight += (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth); -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

The associated patch caused a compilation problems on Hexagon: https://bugs.llvm.org/show_bug.cgi?id=43302 The splitting of a live interval should not be done automatically upon creation. Calling LIS->getInterval(Reg) should not go around changing the code behind the scenes. There is already a function “splitSeparateComponents” that does that. It should be added where it’s missing. -- Krzysztof Parzyszek kparzysz at quicinc.com<mailto:kparzysz at quicinc.com> AI tools development From: llvm-d...

...erator Units(Reg, &TRI); Units.isValid(); ++Units) if (LiveInterval *LI = LIS.getCachedRegUnit(*Units)) collectRanges(MO, LI, Entering, Internal, Exiting, OldIdx); } else { // Collect ranges for individual virtual registers. collectRanges(MO, &LIS.getInterval(Reg), Entering, Internal, Exiting, OldIdx); } As an experiment, you could replace getCachedRegUnit with getRegUnit (the uncached version) to make verify we don't have a stale state in the cache. On Thu, Aug 30, 2012 at 3:01 PM, Sergei Larin <slarin at codeaur...

...def) { DEBUG(dbgs() << "orig phi value\n"); SVI->second.DefByOrigPHI = true; SVI->second.AllDefsAreReloads = false; propagateSiblingValue(SVI); continue; } // check if the valno is actually an orig PHI, but is not OrigVNI else { LiveInterval &OrigLI = LIS.getInterval(Original); VNInfo *OrigVNI_curr = OrigLI.getVNInfoAt(VNI->def); if (OrigVNI_curr->def == VNI->def) assert(0 && "OrigLI contained VNI which was a PHI, but not OrigVNI!"); } , but the assert never triggered anywhere else than in my original case. When I did the...

...spilling >>> function. From what I observe, I'd say it is related to >>> rematerializable intervals. >>> >>> The assertion says: >>> /opt/llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h:142: >>> llvm::LiveInterval& llvm::LiveIntervals::getInterval(unsigned int): >>> Assertion `I != r2iMap_.end() && "Interval does not exist for >>> register"' failed. >>> >>> I attach the BC file generated by bugpoint, so that you can >>> reproduce it. >>> >>> The command-...

...gic): for (LiveIntervals::const_iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) { unsigned VirtReg = I->first; if ((TargetRegisterInfo::isVirtualRegister(VirtReg)) && (VRM->getPhys(VirtReg) == REG_Y)) { LiveInterval &LI = LIS->getInterval(VirtReg); unassign(LI, REG_Y); enqueue(&LI); } } RegClassInfo.runOnMachineFunction(VRM->getMachineFunction()); // update reserve reglist So similar to what's done in LRE_WillShrinkVirtReg(), it searches for live intervals where REG_Y is allocated and evicts them for...

...def) { DEBUG(dbgs() << "orig phi value\n"); SVI->second.DefByOrigPHI = true; SVI->second.AllDefsAreReloads = false; propagateSiblingValue(SVI); continue; } // check if the valno is actually an orig PHI, but is not OrigVNI else { LiveInterval &OrigLI = LIS.getInterval(Original); VNInfo *OrigVNI_curr = OrigLI.getVNInfoAt(VNI->def); if (OrigVNI_curr->def == VNI->def) assert(0 && "OrigLI contained VNI which was a PHI, but not OrigVNI!"); } , but the assert never triggered anywhere else than in my original case. When I did the...

...mp;TRI); Units.isValid(); ++Units) > if (LiveInterval *LI = LIS.getCachedRegUnit(*Units)) > collectRanges(MO, LI, Entering, Internal, Exiting, OldIdx); > } else { > // Collect ranges for individual virtual registers. > collectRanges(MO, &LIS.getInterval(Reg), > Entering, Internal, Exiting, OldIdx); > } > > As an experiment, you could replace getCachedRegUnit with getRegUnit > (the uncached version) to make verify we don't have a stale state in > the cache. LIS.getRegUnit() will either return the...

...-MT mf-heuristics.lo -MD -MP -MF .deps/mf-heuristics.Tpo -c /tmp/llvm-project.p28262/src/llvm-gcc-4.2/libmudflap/mf-heuristics.c -fPIC -DPIC -o .libs/mf-heuristics.o cc1: /tmp/llvm-project.p28262/src/llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h:134: llvm::LiveInterval& llvm::LiveIntervals::getInterval(unsigned int): Assertion `I != r2iMap_.end() && "Interval does not exist for register"' failed. /tmp/llvm-project.p28262/src/llvm-gcc-4.2/libmudflap/mf-heuristics.c:175: internal compiler error: Aborted Please submit a full bug report, with preprocessed source if appropriate...

On Jun 11, 2009, at 7:18 PM, Misha Brukman wrote: > I've committed my scripts that simplify building Linux/x86 -> Linux/ > ARM crosstool. There are 2 parts to using this: > > * llvm/utils/crosstool/create-snapshots.sh > creates tarballs for LLVM and LLVM-GCC from HEAD SVN or a specific > revision of your choice > * llvm/utils/crosstool/ARM/build-install-linux.sh

...continue; if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { if (MRI.isConstantPhysReg(MO.getReg(), *DefMI->getParent()->getParent())) continue; //If not constant then check its def if(depth > 6) return false; LiveInterval &li = LIS.getInterval(MO.getReg()); SlotIndex UseIdx = LIS.getInstructionIndex(*DefMI); VNInfo *UseVNInfo = li.getVNInfoAt(UseIdx); MachineInstr *NewDefMI = LIS.getInstructionFromIndex(UseVNInfo->def); if(!checkComplexRematerializable(UseVNInfo, NewDefMI, depth+1, aa)) return false;...

...iterator I = LIS->begin(), E = LIS->end(); I != E; > ++I) > { > unsigned VirtReg = I->first; > if ((TargetRegisterInfo::isVirtualRegister(VirtReg)) > && (VRM->getPhys(VirtReg) == REG_Y)) > { > LiveInterval &LI = LIS->getInterval(VirtReg); > unassign(LI, REG_Y); > enqueue(&LI); > } > } > RegClassInfo.runOnMachineFunction(VRM->getMachineFunction()); // update reserve reglist > > So similar to what's done in LRE_WillShrinkVirtReg(), it searches for live intervals where REG_...

...g() && > MRegisterInfo::isVirtualRegister(mop.getReg())) { > // replace register with representative register > unsigned reg = rep(mop.getReg()); > mii->SetMachineOperandReg(i, reg); > > LiveInterval &RegInt = getInterval(reg); > RegInt.weight += > (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth); > > -Chris -- http://nondot.org/sabre/ http://llvm.org/

...mp;& > MRegisterInfo::isVirtualRegister(mop.getReg())) { > // replace register with representative register > unsigned reg = rep(mop.getReg()); > mii->SetMachineOperandReg(i, reg); > > LiveInterval &RegInt = getInterval(reg); > RegInt.weight += > (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth); > After joining intervals some moves are unecessary. If for example this instruction was in the code: mov %reg1024, %reg1045 and intervals for reg1024 and reg1045 were joine...