Displaying 20 results from an estimated 22 matches for "getinstr".
2018 May 09
2
[MachineScheduler] Question about IssueWidth / NumMicroOps
...iously scheduled here. I then again
would say (1). (Checking for decoder groups
pre-RA does BTW not make much sense on SystemZ, but that's another
question).
checkHazard() also return hazard if
(CurrMOps > 0 &&
((isTop() && SchedModel->mustBeginGroup(SU->getInstr())) ||
(!isTop() && SchedModel->mustEndGroup(SU->getInstr()))))
, which also per the same lines makes me think that this is intended for
the instruction stream management, or (1).
There is also the fact that
IsResourceLimited =
checkResourceLimit(SchedModel->getL...
2012 Aug 28
2
[LLVMdev] Assert in LiveInterval update
...hen you were out of town... I think
I am getting more context on it. Please take a look...
So, in short, when the new MI scheduler performs move of an instruction, it
does something like this:
// Move the instruction to its new location in the instruction stream.
MachineInstr *MI = SU->getInstr();
if (IsTopNode) {
assert(SU->isTopReady() && "node still has unscheduled dependencies");
if (&*CurrentTop == MI) <<<<<<<<<<<<<<<<<< Here we make
sure that CurrentTop != MI.
Curre...
2012 Aug 28
0
[LLVMdev] Assert in LiveInterval update
...nk
> I am getting more context on it. Please take a look...
>
> So, in short, when the new MI scheduler performs move of an instruction, it
> does something like this:
>
> // Move the instruction to its new location in the instruction stream.
> MachineInstr *MI = SU->getInstr();
>
> if (IsTopNode) {
> assert(SU->isTopReady() && "node still has unscheduled dependencies");
> if (&*CurrentTop == MI) <<<<<<<<<<<<<<<<<< Here we make
> sure that CurrentTop...
2012 Aug 28
5
[LLVMdev] Assert in LiveInterval update
...on it. Please take a look...
> >
> > So, in short, when the new MI scheduler performs move of an
> > instruction, it does something like this:
> >
> > // Move the instruction to its new location in the instruction
> stream.
> > MachineInstr *MI = SU->getInstr();
> >
> > if (IsTopNode) {
> > assert(SU->isTopReady() && "node still has unscheduled
> dependencies");
> > if (&*CurrentTop == MI) <<<<<<<<<<<<<<<<<< Here we
> m...
2018 May 09
0
[MachineScheduler] Question about IssueWidth / NumMicroOps
...hen again would say (1). (Checking for decoder groups
> pre-RA does BTW not make much sense on SystemZ, but that's another question).
>
> checkHazard() also return hazard if
>
> (CurrMOps > 0 &&
> ((isTop() && SchedModel->mustBeginGroup(SU->getInstr())) ||
> (!isTop() && SchedModel->mustEndGroup(SU->getInstr()))))
>
> , which also per the same lines makes me think that this is intended for the instruction stream management, or (1).
>
> There is also the fact that
>
> IsResourceLimited =
> c...
2012 Aug 30
0
[LLVMdev] Assert in LiveInterval update
...> >
> > > So, in short, when the new MI scheduler performs move of an
> > > instruction, it does something like this:
> > >
> > > // Move the instruction to its new location in the instruction
> > stream.
> > > MachineInstr *MI = SU->getInstr();
> > >
> > > if (IsTopNode) {
> > > assert(SU->isTopReady() && "node still has unscheduled
> > dependencies");
> > > if (&*CurrentTop == MI) <<<<<<<<<<<<<<<<...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...rite to the virtual register defined at OperIdx.
///
/// TODO: Hoist loop induction variable increments. This has to be
/// reevaluated. Generally, IV scheduling should be done before coalescing.
void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
const MachineInstr *MI = SU->getInstr();
unsigned Reg = MI->getOperand(OperIdx).getReg();
// SSA defs do not have output/anti dependencies.
// The current operand is a def, so we have at least one.
if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) <<<<<<<<<<<<<<<<<<...
2012 Aug 31
2
[LLVMdev] Assert in LiveInterval update
...on it. Please take a look...
> >
> > So, in short, when the new MI scheduler performs move of an
> > instruction, it does something like this:
> >
> > // Move the instruction to its new location in the instruction
> stream.
> > MachineInstr *MI = SU->getInstr();
> >
> > if (IsTopNode) {
> > assert(SU->isTopReady() && "node still has unscheduled
> dependencies");
> > if (&*CurrentTop == MI) <<<<<<<<<<<<<<<<<< Here we
> m...
2014 Dec 14
2
[LLVMdev] ScheduleDAGInstrs.cpp
...endency on the new AliasChain.
Or am I missing something? Very interested in your opinion.
I am thinking of something like
new_alias_chain:
// Chain all possibly aliasing memory references through SU.
if (AliasChain) {
unsigned ChainLatency = 0;
if (AliasChain->getInstr()->mayLoad()) ChainLatency = TrueMemOrderLatency;
addChainDependency(AAForDep, MFI, SU, AliasChain, RejectMemNodes,
ChainLatency);
+
+ // Since TII->areMemAccessesTriviallyDisjoint() is not
+ // complete, iterate all chain successor...
2012 Aug 30
0
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...> >
> > > So, in short, when the new MI scheduler performs move of an
> > > instruction, it does something like this:
> > >
> > > // Move the instruction to its new location in the instruction
> > stream.
> > > MachineInstr *MI = SU->getInstr();
> > >
> > > if (IsTopNode) {
> > > assert(SU->isTopReady() && "node still has unscheduled
> > dependencies");
> > > if (&*CurrentTop == MI) <<<<<<<<<<<<<<<<...
2014 Dec 08
3
[LLVMdev] ScheduleDAGInstrs.cpp
Hi,
Can anyone help me to understand the ScheduleDAGInstrs::buildSchedGraph() method?
I find the handling of AliasChain is disturbing since:
1. A new alias chain add deps to all possibly aliasing SUs, and then clears those lists.
2. When AliasChain is present, the addChainDependency() method is called,
but the target hook areMemAccessesTriviallyDisjoint() called inside
2012 Aug 31
0
[LLVMdev] Assert in LiveInterval update
...*Roots;
for (MachineRegisterInfo::use_nodbg_iterator
UI = MRI.use_nodbg_begin(Root),
UE = MRI.use_nodbg_end();
UI != UE; UI.skipInstruction()) {
const MachineInstr* MI = &*UI;
SlotIndex InstSlot =
LIS.getSlotIndexes()->getInstructionIndex(MI);
if (InstSlot > LastUse && InstSlot < OldIdx)
LastUse = InstSlot;
}
//for (MCSuperRegIterator Supers(Root, &TRI); Supers.isValid();
++Supers)
// I do not think we should be doing this here.
}
} else {...
2019 Jan 31
2
MachineIRBuilder API
I’m less interested in literally passing the output of one as an argument to the next such that argument evaluation order matters. Intermediate register variables are fine. It would still be less code to have tmp = buildFoo(), buildFoo(tmp) than the current code required to manage the register
-Matt
From: <daniel_l_sanders at apple.com> on behalf of Daniel Sanders <daniel_l_sanders at
2012 Aug 30
2
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...> So, in short, when the new MI scheduler performs move of an
>> > > instruction, it does something like this:
>> > >
>> > > // Move the instruction to its new location in the instruction
>> > stream.
>> > > MachineInstr *MI = SU->getInstr();
>> > >
>> > > if (IsTopNode) {
>> > > assert(SU->isTopReady() && "node still has unscheduled
>> > dependencies");
>> > > if (&*CurrentTop == MI) <<<<<<<<<<<...
2012 Aug 17
0
[LLVMdev] Assert in LiveInterval update
Andy, Jacob,
I have ported Hexagon MI scheduler to use the new scheduler
infrastructure, but one of my tests triggers an assert in LiveInterval
update. On the surface it does not make much sense to me, so I wonder if
this is something you readily recognize, before I try to prop it open...
The assert is:
lib/CodeGen/LiveInterval.cpp:266: llvm::LiveRange*
2012 Jun 13
4
[LLVMdev] Assert in live update from MI scheduler.
Andy,
Thanks for reply. I was able to trace the problem to the MI DAG dep
constructor. See this:
SU(0): %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
# preds left : 0
# succs left : 0
# rdefs left : 1
Latency : 1
Depth : 0
Height : 0
SU(1): %vreg10<def> = LDriw %vreg9<kill>, 0;
2014 Dec 16
3
[LLVMdev] ScheduleDAGInstrs.cpp
...am I missing something? Very interested in your opinion.
>
> I am thinking of something like
>
> new_alias_chain:
> // Chain all possibly aliasing memory references through SU.
> if (AliasChain) {
> unsigned ChainLatency = 0;
> if (AliasChain->getInstr()->mayLoad()) ChainLatency = TrueMemOrderLatency;
> addChainDependency(AAForDep, MFI, SU, AliasChain, RejectMemNodes,
> ChainLatency);
> +
> + // Since TII->areMemAccessesTriviallyDisjoint() is not
> + // complete, iter...
2012 Aug 30
0
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...w MI scheduler performs move of an
> >> > > instruction, it does something like this:
> >> > >
> >> > > // Move the instruction to its new location in the
> instruction
> >> > stream.
> >> > > MachineInstr *MI = SU->getInstr();
> >> > >
> >> > > if (IsTopNode) {
> >> > > assert(SU->isTopReady() && "node still has unscheduled
> >> > dependencies");
> >> > > if (&*CurrentTop == MI) <<<<&l...
2012 Sep 03
2
[LLVMdev] Assert in LiveInterval update
...;
> UI = MRI.use_nodbg_begin(Root),****
>
> UE = MRI.use_nodbg_end();****
>
> UI != UE; UI.skipInstruction()) {****
>
> const MachineInstr* MI = &*UI;****
>
> SlotIndex InstSlot =
> LIS.getSlotIndexes()->getInstructionIndex(MI);****
>
> if (InstSlot > LastUse && InstSlot < OldIdx) ****
>
> LastUse = InstSlot;****
>
> }****
>
> //for (MCSuperRegIterator Supers(Root, &TRI); Supers.isValid();
> ++Supers) ****
>
> //...
2012 Aug 15
3
[LLVMdev] MI bundle liveness attributes
On Aug 13, 2012, at 8:34 AM, Sergei Larin <slarin at codeaurora.org> wrote:
> Andy,
>
> Yes, this is what Arnold has suggested also, and from this point it looks
> like it should work, but it will require parsing the bundle every time we
> care to know whether this is a real use or a conditional def. This might
> become awkward... but I guess I should provide a better