search for: getindirectr

Displaying 3 results from an estimated 3 matches for "getindirectr".

Did you mean: getindirect
2014 Aug 08
2
[PATCH 1/3] nvc0/ir: add base tex offset for fermi indirect tex case
...u/codegen/nv50_ir_lowering_nvc0.cpp index f010767..4a9e48f 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp @@ -603,10 +603,18 @@ NVC0LoweringPass::handleTEX(TexInstruction *i) Value *ticRel = i->getIndirectR(); Value *tscRel = i->getIndirectS(); - if (ticRel) + if (ticRel) { i->setSrc(i->tex.rIndirectSrc, NULL); - if (tscRel) + if (i->tex.r) + ticRel = bld.mkOp2v(OP_ADD, TYPE_U32, bld.getScratch(), + ticRel,...
2014 Sep 25
0
[PATCH] gm107/ir: fix texture argument order
...Src(dim, layer); + } } // Move the indirect reference to the first place - if (i->tex.rIndirectSrc >= 0) { + if (i->tex.rIndirectSrc >= 0 && ( + i->op == OP_TXD || chipset < NVISA_GM107_CHIPSET)) { Value *hnd = i->getIndirectR(); i->setIndirectR(NULL); @@ -742,8 +762,10 @@ NVC0LoweringPass::handleTEX(TexInstruction *i) // create it if it's not already there, and INSBF it if it already // is. s = (i->tex.rIndirectSrc >= 0) ? 1 : 0; + if (chipset &g...
2019 Oct 14
1
[PATCH] gm107/ir: fix loading z offset for layered 3d image bindings
...int slot = su->tex.r; const int dim = su->tex.target.getDim(); - const int arg = dim + (su->tex.target.isArray() || su->tex.target.isCube()); + const bool array = su->tex.target.isArray() || su->tex.target.isCube(); + const int arg = dim + array; Value *ind = su->getIndirectR(); Value *handle; + Instruction *pred = NULL, *pred2d = NULL; int pos = 0; bld.setPosition(su, false); @@ -2489,67 +2511,153 @@ NVC0LoweringPass::processSurfaceCoordsGM107(TexInstruction *su) assert(pos == 0); break; } + + if (dim == 2 && !array) { +...