Displaying 10 results from an estimated 10 matches for "getimplicitdef".
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getimplicitdefs
2019 Nov 19
2
Question about physical registers in ISel
...of outputs of a MachineSDNode is greater than the number of defs
in the corresponding MCInstrDesc, the outputs in the difference will be
placed into physical registers as opposed to virtual registers.
The specific line in question is:
bool HasPhysRegOuts = NumResults > NumDefs &&
II.getImplicitDefs()!=nullptr;
Where NumResults is the number of outputs in the MachineSDNode and NumDefs
comes from the MCInstrDesc and ultimately the TableGen definition of the
instruction. I do not know why this assumption is made or what code depends
on it, but it is over 12 years old:
https://github.com/llvm/l...
2019 Nov 19
2
Question about physical registers in ISel
...is greater than the number of defs
> in the corresponding MCInstrDesc, the outputs in the difference will be
> placed into physical registers as opposed to virtual registers.
>
> The specific line in question is:
> bool HasPhysRegOuts = NumResults > NumDefs &&
> II.getImplicitDefs()!=nullptr;
>
> Where NumResults is the number of outputs in the MachineSDNode and NumDefs
> comes from the MCInstrDesc and ultimately the TableGen definition of the
> instruction. I do not know why this assumption is made or what code depends
> on it, but it is over 12 years old:
&...
2019 Nov 19
2
Question about physical registers in ISel
...ber of defs
>> in the corresponding MCInstrDesc, the outputs in the difference will be
>> placed into physical registers as opposed to virtual registers.
>>
>> The specific line in question is:
>> bool HasPhysRegOuts = NumResults > NumDefs &&
>> II.getImplicitDefs()!=nullptr;
>>
>> Where NumResults is the number of outputs in the MachineSDNode and
>> NumDefs comes from the MCInstrDesc and ultimately the TableGen definition
>> of the instruction. I do not know why this assumption is made or what code
>> depends on it, but it is...
2019 Nov 20
2
Question about physical registers in ISel
...in the corresponding MCInstrDesc, the outputs in the difference will be
>>> placed into physical registers as opposed to virtual registers.
>>>
>>> The specific line in question is:
>>> bool HasPhysRegOuts = NumResults > NumDefs &&
>>> II.getImplicitDefs()!=nullptr;
>>>
>>> Where NumResults is the number of outputs in the MachineSDNode and
>>> NumDefs comes from the MCInstrDesc and ultimately the TableGen definition
>>> of the instruction. I do not know why this assumption is made or what code
>>> depen...
2009 Oct 22
4
[LLVMdev] request for help writing a register allocator
...you will probably have some errors. My
apologies for not mentioning this earlier.
You can find the set of implicit uses and defs by querying the
TargetInstDesc object for each MachineInstr (call MachineInstr::getDesc() to
get it, and then the TargetInstrDesc::getImplicitUses() and
TargetInstrDesc::getImplicitDefs() methods to find the regs used/definied by
this instr).
2) How are you making sure that interfering virtregs never receive the same
physreg? If you're using the LiveIntervals analysis (and the
LiveInterval::overlaps(LiveInterval &) test) you should be ok, since it gets
a lot of testing (...
2009 Oct 22
0
[LLVMdev] request for help writing a register allocator
...rrors.
> My apologies for not mentioning this earlier.
>
> You can find the set of implicit uses and defs by querying the
> TargetInstDesc object for each MachineInstr (call MachineInstr::getDesc() to
> get it, and then the TargetInstrDesc::getImplicitUses() and
> TargetInstrDesc::getImplicitDefs() methods to find the regs used/definied by
> this instr).
>
Oops. Seems we copy implicit operands like this into MachineOperands on the
instruction before register allocation. Disregard the above advice - you do
not need to check the TargetInstrDesc implicit operands. You only need to
chec...
2010 Apr 16
1
[LLVMdev] Delay Slot Filler
> You have to create one! Take a look at PPCHazardRecognizers.cpp
> and SPUHazardRecognizers.cpp for examples.
> If you can, contribute it back! :)
There is also generic hazard recognizer which works on top of
instruction itineraries.
--
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University
2017 Feb 14
2
Adding FP environment register modeling for constrained FP nodes
...e that was entirely possible. I’ll try adding implicit defs in the way you’ve suggested, but I’m concerned that there may be code that relies on the TII for that kind of thing -- for instance, InstrEmitter::EmitMachineNode() does this:
bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr;
where “NumDefs” comes from TII and “NumResults” comes from the node. Obviously we can fix that up as needed, but it seems like a weak point in the design. Perhaps it is still better than trying to maintain a duplicate set of opcodes though.
I’m still trying to piece together how to...
2009 Oct 21
0
[LLVMdev] request for help writing a register allocator
Lang -
I've made some progress writing my register allocator, but now I'm stuck.
I have 2 questions for you:
1. I tried running the PBQP allocator (as a dynamic pass), but that didn't
work. When I type this:
llc -f -load Debug/lib/regalloc.so -regalloc=pbqp simple.bc
I get the following error:
llc:
2009 Oct 20
7
[LLVMdev] request for help writing a register allocator
Hi Susan,
> You may find the PBQP allocator implementation useful as a reference
> to what's involved in adding a new allocator to LLVM. It's located in
> lib/CodeGen/RegAllocPBQP.cpp, with supporting files in the lib/CodeGen/
> PBQP directory.
>
Yes - as far as working allocators go PBQP is pretty simple. If you're just
interested in LLVM API details you can focus on