search for: getimm

...tPrinter.cpp @@ -44,17 +44,18 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) { const MCOperand &MO2 = MI->getOperand(2); const MCOperand &MO3 = MI->getOperand(3); - O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); + O << '\t' << "mov"; printSBitModifierOperand(MI, 6, O); printPredicateOperand(MI, 4, O); O << '\t' << getRegisterName(Dst.getReg()) - << ", " << getRegisterName(MO1.getReg()); + << &qu...

On Jun 22, 2011, at 9:00 AM, Renato Golin wrote: > On 22 June 2011 16:50, Jim Grosbach <grosbach at apple.com> wrote: >>> This sounds like a dead end as newer binutils are GPLv3. >> >> Yeah, that's definitely a very real concern and a big motivation to get the MC based asm parser whipped into usable shape. We're much more in control of our own destiny then.

...    if (ByteValues.size()-1-DestByteNo != InputByteNo)       return true;   } Note that 'then' and 'else' are the same. It can be a problem or can not. ---- lib/Target/X86/InstPrinter/X86InstComments.cpp:208   case X86::VPERMILPSri:     DecodeVPERMILPSMask(4, MI->getOperand(2).getImm(),                         ShuffleMask);     Src1Name = getRegName(MI->getOperand(0).getReg());   case X86::VPERMILPSYri:     DecodeVPERMILPSMask(8, MI->getOperand(2).getImm(),                         ShuffleMask);     Src1Name = getRegName(MI->getOperand(0).getReg()); The 'Src1Name...

..." > +#include "llvm/Target/TargetAsmInfo.h" > using namespace llvm; > > extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See > PPCRegisterInfo.cpp. > @@ -724,3 +725,21 @@ > > Cond > [0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); > return false; > } > + > +/// GetInstSize - Return the number of bytes of code the specified > +/// instruction may be. This returns the maximum number of bytes. > +/// > +unsigned PPCInstrInfo::GetInstSize(const MachineInstr *MI) const { > + switch (MI->getOpco...

OK, here's a new patch that adds the infrastructure and the implementation for X86, ARM and PPC of GetInstSize and GetFunctionSize. Both functions are virtual functions defined in TargetInstrInfo.h. For X86, I moved some commodity functions from X86CodeEmitter to X86InstrInfo. What do you think? Nicolas Evan Cheng wrote: > > I think both of these belong to TargetInstrInfo. And

...ransform constant SDNodes into other values. For a worked example, in the MIPS backend we use this for constant synthesis by materializing the value into a register: (From lib/Target/MipsInstrInfo.td): // Transformation Function - get the lower 16 bits. def LO16 : SDNodeXForm<imm, [{ return getImm(N, N->getZExtValue() & 0xFFFF); }]>; The above fragment will take an immediate node and get the lower 16 bits. // Transformation Function - get the higher 16 bits. def HI16 : SDNodeXForm<imm, [{ return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); }]>; Similarly,...

On Tue, Apr 08, 2014 at 04:08:13PM +0400, Robert Khasanov wrote: > Hi Reid, > > Would you approve your patches r203146 and r202774 to be backported to > 3.4.1? They fix stability issues in x86 asm. > Hi Robert, I was able to merge r203146, but it used a c++11 feature: std::string::back() which I replaced with std::string::at(std::string::size() - 1). r202774 was not merged,

Hi all, This seems like a dumb question but while setting up a pattern in TD file, I got stuck on trying to get each half of an immediate as the half-sized type (ie. i64 imm -> pair of i32 imm's). Is there an existing way to do it? I've tried the 'EXTRACT_SUBREG' but that seems to error at the end of scheduling. Looking at Target.td, I'm not sure which opcode is meant

...Reg()) { + unsigned IndexReg16 = R16Table[GetX86RegNum(IndexReg)]; + + // Must have one of SI,DI (4,5), and one of BP/BX (6,7) + assert(((IndexReg16 ^ RMfield) & 2) && + "invalid 16-bit base/index register combination"); + assert(Scale.getImm() == 1 && + "invalid scale for 16-bit memory reference"); + + if (IndexReg16 & 2) + RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1); + else + RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1); + } + +...

...d IndexReg16 = R16Table[GetX86RegNum(IndexReg)]; > + > + // Must have one of SI,DI (4,5), and one of BP/BX (6,7) > + assert(((IndexReg16 ^ RMfield) & 2) && > + "invalid 16-bit base/index register combination"); > + assert(Scale.getImm() == 1 && > + "invalid scale for 16-bit memory reference"); > + > + if (IndexReg16 & 2) > + RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1); > + else > + RMfield = (IndexReg16 & 1) | ((7 - RMfield)...

...MachineOperand Dst = MI->getOperand(0); MachineOperand TrueVal = MI->getOperand(1); MachineOperand FalseVal = MI->getOperand(2); MachineOperand CCFlag = MI->getOperand(3); CC = (INSTCC::CondCodes)MI->getOperand(3).getImm(); // Here I want to get the destination register of SET_CC instruction and place it as the first addReg TODO(Get setcc destination register); BuildMI(BB, TII.get(INST::CMOVLOG_32),Dst.getReg()).addReg(CCFlag.getImm()).addReg(T rueVal.getReg()).addReg(FalseVal.get...

...44,17 +44,18 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) { > const MCOperand &MO2 = MI->getOperand(2); > const MCOperand &MO3 = MI->getOperand(3); > > - O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); > + O << '\t' << "mov"; > printSBitModifierOperand(MI, 6, O); > printPredicateOperand(MI, 4, O); > > O << '\t' << getRegisterName(Dst.getReg()) > - << ", " << getRegisterName(MO1.getR...

...PFISelLowering.cpp > @@ -578,11 +578,15 @@ > BPFTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, > .addReg(LHS) > .addReg(MI.getOperand(2).getReg()) > .addMBB(Copy1MBB); > - else > + else { > + int64_t imm32 = MI.getOperand(2).getImm(); > + // sanity check before we build J*_ri instruction. > + assert (isInt<32>(imm32)); > BuildMI(BB, DL, TII.get(NewCC)) > .addReg(LHS) > - .addImm(MI.getOperand(2).getImm()) > + .addImm(imm32) > .addMBB(Copy1MBB); > + } &g...

..., TII->get(ARM::B)).addMBB(trgBlock); these are working fine. When creating an compare instruction like cmp r0, 1 with:      BuildMI(BB, BB.end(), DL, TII->get(ARM::tCMPi8),0).addImm(1); I get the following error:     .../include/llvm/MC/MCInst.h:81: int64_t llvm::MCOperand::getImm() const: Assertion `isImm() && "This is not an immediate"' failed. Which even after hours I can't make sense why the operand kind is wrong. Another thing I noticed is that using ARM::tB results in the following error: .../include/llvm/ADT/SmallVector.h:154: con...

...I notice that the following recent addition X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) { switch (MI.getOpcode()) { default: return X86::COND_INVALID; case X86::JCC_1: return static_cast<X86::CondCode>( MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm()); } } returns an invalid condition for JCC_2 and JCC_4 conditional opcodes. What is the suggested way to figure out the condition code for JCC_2 and JCC_4? Should I just roll one up for myself to handle such opcodes based on the above? Am I missing something conceptually? Thanks, Bharadwaj

...etOperand(OpNo); - const MachineOperand &MO2 = MI->getOperand(OpNo+1); // Unique Id - unsigned JTI = MO1.getIndex(); - O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() - << '_' << JTI << '_' << MO2.getImm() << ":\n"; + std::stringstream prefix; + + const unsigned JTI = MI->getOperand(OpNo).getIndex(); + const unsigned uid = MI->getOperand(OpNo+1).getImm(); + + if (FlagOutlineJumpTables) { + // needs to be synchronized with ARMConstantPoolValue.cpp + prefix <<...

...ot;) || Name.endswith("l") || Name.endswith("q")) + && Operands.size() == 3) { + X86Operand &Op1 = *(X86Operand*)Operands.begin()[1]; + X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; + + if (Op1.isImm() && isa<MCConstantExpr>(Op1.getImm()) && + Op2.isMem() && isa<MCConstantExpr>(Op2.Mem.Disp)) { + int64_t Given_imm = cast<MCConstantExpr>(Op1.getImm())->getValue(); + int64_t Given_mem = cast<MCConstantExpr>(Op2.Mem.Disp)->getValue(); + + static_cast<X86Operand*>(Operands[...

...e that 'then' and 'else' are the same. It can be a problem or can not. I've CC'd Chris since he wrote this code. > > ---- > > lib/Target/X86/InstPrinter/X86InstComments.cpp:208 > case X86::VPERMILPSri: > DecodeVPERMILPSMask(4, MI->getOperand(2).getImm(), > ShuffleMask); > Src1Name = getRegName(MI->getOperand(0).getReg()); > case X86::VPERMILPSYri: > DecodeVPERMILPSMask(8, MI->getOperand(2).getImm(), > ShuffleMask); > Src1Name = getRegName(MI->getOperan...

...X86::BT32ri8: case X86::BT16ri8: { assert(OldMI->getNumOperands() >= 2); MachineOperand &Reg = OldMI->getOperand(0); MachineOperand &Imm = OldMI->getOperand(1); assert(Reg.isReg()); assert(Imm.isImm()); imm = Imm.getImm(); if (imm >= 32) continue; kill = getKillRegState(Reg.isKill()); switch (Reg.getReg()) { default: assert(false); case X86::RAX: case X86::EAX: case X86::AX: if (imm < 8) NewMI...

On Jun 8, 2009, at 2:42 PM, robert muth wrote: > On Sun, Jun 7, 2009 at 11:53 PM, Evan Cheng <evan.cheng at apple.com> > wrote: >> >> On Jun 7, 2009, at 6:59 AM, robert muth wrote: >> >>> On Sat, Jun 6, 2009 at 4:51 PM, Evan Cheng<evan.cheng at apple.com> >>> wrote: >>>> +cl::opt<std::string>