Displaying 18 results from an estimated 18 matches for "getframelow".
2011 Aug 24
1
[LLVMdev] Segmented Stacks (re-roll)
...pp
index 5ffb8f2..cc2ca87 100644
--- a/lib/CodeGen/StackSegmenter.cpp
+++ b/lib/CodeGen/StackSegmenter.cpp
@@ -40,7 +40,10 @@ void StackSegmenter::getAnalysisUsage(AnalysisUsage
&info) const {
}
bool StackSegmenter::runOnMachineFunction(MachineFunction &MF) {
- return false;
+ const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
+ TFI.adjustForSegmentedStacks(MF);
+ // adjustForSegmentedStacks always changes the MachineFunction
+ return true;
}
FunctionPass *llvm::createStackSegmenter() {
--
Sanjoy Das
http://playingwithpointers.com
2013 Sep 25
2
[LLVMdev] Register scavenger and SP/FP adjustments
...const TargetMachine &TM = Fn.getTarget();
assert(TM.getRegisterInfo() &&
"TM::getRegisterInfo() must be implemented!");
const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
const TargetFrameLowering *TFI = TM.getFrameLowering();
bool StackGrowsDown =
TFI->getStackGrowthDirection() ==
TargetFrameLowering::StackGrowsDown;
int FrameSetupOpcode = TII.getCallFrameSetupOpcode();
int FrameDestroyOpcode = TII.getCallFrameDestroyOpcode();
if (RS && !...
2011 Oct 11
1
[LLVMdev] Expected behavior of eliminateFrameIndex() on dbg_value machine instructions
...hineOperand RegOp = DVInsn->getOperand(0);
const TargetRegisterInfo *TRI = Asm->TM.getRegisterInfo();
if (DVInsn->getOperand(1).isImm() &&
TRI->getFrameRegister(*Asm->MF) == RegOp.getReg()) {
unsigned FrameReg = 0;
const TargetFrameLowering *TFI = Asm->TM.getFrameLowering();
int Offset =
TFI->getFrameIndexReference(*Asm->MF,
DVInsn->getOperand(1).getImm(),
FrameReg);
MachineLocation Location(FrameReg, O...
2013 Sep 26
0
[LLVMdev] Register scavenger and SP/FP adjustments
...Machine &TM = Fn.getTarget();
> assert(TM.getRegisterInfo() &&
> "TM::getRegisterInfo() must be implemented!");
> const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
> const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
> const TargetFrameLowering *TFI = TM.getFrameLowering();
> bool StackGrowsDown =
> TFI->getStackGrowthDirection() ==
> TargetFrameLowering::StackGrowsDown;
> int FrameSetupOpcode = TII.getCallFrameSetupOpcode();
> int FrameDestroyOpcode = TII.getCallFrameDestroyOpcode();
>
&g...
2011 Aug 23
0
[LLVMdev] Segmented Stacks (re-roll)
On Aug 23, 2011, at 9:24 AM, Sanjoy Das wrote:
> Hi!
>
>> diff --git a/lib/CodeGen/StackSegmenter.cpp b/lib/CodeGen/StackSegmenter.cpp
>> new file mode 100644
>> index 0000000..5ffb8f2
>> --- /dev/null
>> +++ b/lib/CodeGen/StackSegmenter.cpp
>> @@ -0,0 +1,48 @@
>> +//===-- StackSegmenter.h - Prolog/Epilog code insertion -------*- C++ -* --===//
2011 Aug 23
2
[LLVMdev] Segmented Stacks (re-roll)
Hi!
> diff --git a/lib/CodeGen/StackSegmenter.cpp b/lib/CodeGen/StackSegmenter.cpp
> new file mode 100644
> index 0000000..5ffb8f2
> --- /dev/null
> +++ b/lib/CodeGen/StackSegmenter.cpp
> @@ -0,0 +1,48 @@
> +//===-- StackSegmenter.h - Prolog/Epilog code insertion -------*- C++ -* --===//
>
> The comment is obviously incorrect.
Thanks. So much for lifting file
2011 Oct 10
0
[LLVMdev] Expected behavior of eliminateFrameIndex() on dbg_value machine instructions
On Oct 10, 2011, at 10:26 AM, Richard Osborne wrote:
> I'm investigating a bug associated with debug information that manifests
> itself in the XCore backend (PR11105). I'd like to understand what the
> expected behavior of eliminateFrameIndex() is when it is called on a
> dbg_value machine instruction.
That is up to the target.
The TII::emitFrameIndexDebugValue() hook is
2011 Jun 15
0
[LLVMdev] Custom allocation orders
...Subtarget<X86Subtarget>();
if (Subtarget.is64Bit())
return X86_GR8_AO_64;
else
return begin();
}
GR8Class::iterator
GR8Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetFrameLowering *TFI = TM.getFrameLowering();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
// Does the function dedicate RBP / EBP to being a frame ptr?
if (!Subtarget.is64Bit(...
2011 Oct 10
2
[LLVMdev] Expected behavior of eliminateFrameIndex() on dbg_value machine instructions
I'm investigating a bug associated with debug information that manifests
itself in the XCore backend (PR11105). I'd like to understand what the
expected behavior of eliminateFrameIndex() is when it is called on a
dbg_value machine instruction.
Currently the XCore target replaces the frame index with the frame
register and sets the next operand to the byte offset from the frame
2013 Oct 12
3
[LLVMdev] [RFC] CodeGen Context
...ck-end objects themselves (e.g., `use-soft-float').
--------------------------------------------------------------------------------
Before we get further, here are a few definitions used in this document:
Back-end Objects ::
Objects that affect code generation --- e.g., TargetInstrInfo,
TargetFrameLowering, DataLayout, etc.
CGContext ::
A central repository for back-end objects. The back-end objects may change, so
they should not be "cached" by individual passes. This is analogous to the
current TargetMachine object. The term "CGContext" is used because it
separates the cur...
2013 Sep 26
2
[LLVMdev] Register scavenger and SP/FP adjustments
....getTarget();
>> assert(TM.getRegisterInfo() &&
>> "TM::getRegisterInfo() must be implemented!");
>> const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
>> const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
>> const TargetFrameLowering *TFI = TM.getFrameLowering();
>> bool StackGrowsDown =
>> TFI->getStackGrowthDirection() ==
>> TargetFrameLowering::StackGrowsDown;
>> int FrameSetupOpcode = TII.getCallFrameSetupOpcode();
>> int FrameDestroyOpcode = TII.getCallFrameDestr...
2013 Sep 26
0
[LLVMdev] Register scavenger and SP/FP adjustments
...gt;>> assert(TM.getRegisterInfo() &&
>>> "TM::getRegisterInfo() must be implemented!");
>>> const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
>>> const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
>>> const TargetFrameLowering *TFI = TM.getFrameLowering();
>>> bool StackGrowsDown =
>>> TFI->getStackGrowthDirection() ==
>>> TargetFrameLowering::StackGrowsDown;
>>> int FrameSetupOpcode = TII.getCallFrameSetupOpcode();
>>> int FrameDestroyOpcode = TII.ge...
2013 Sep 26
1
[LLVMdev] Register scavenger and SP/FP adjustments
...rt(TM.getRegisterInfo() &&
>>>> "TM::getRegisterInfo() must be implemented!");
>>>> const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
>>>> const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
>>>> const TargetFrameLowering *TFI = TM.getFrameLowering();
>>>> bool StackGrowsDown =
>>>> TFI->getStackGrowthDirection() ==
>>>> TargetFrameLowering::StackGrowsDown;
>>>> int FrameSetupOpcode = TII.getCallFrameSetupOpcode();
>>>> int FrameDe...
2013 Oct 13
0
[LLVMdev] [RFC] CodeGen Context
...needs to. This means
> that back-end code won't be able to cache any of the objects the CGContext
> creates (this has already been addressed).
>
> The CGContext can be reached through the MachineFunction object:
>
> CGContext &context = MF->getContext();
> const TargetFrameLowering *TFL = context->getFrameLowering();
>
> if (TFL->getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp) {
> // ...
> }
>
> Currently, the best place to process the function attributes is towards the
> beginning of the `SelectionDAGISel::runOnMachineFunct...
2013 Apr 01
0
[LLVMdev] proposed change to class BasicTTI and dual mode mips16/32 working
...@
#include "MipsSelectionDAGInfo.h"
#include "MipsSubtarget.h"
#include "llvm/ADT/OwningPtr.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetMachine.h"
@@ -35,6 +37,12 @@ class MipsTargetMachine : public LLVMTargetMachine {
OwningPtr<const MipsInstrInfo> InstrInfo;
OwningPtr<const MipsFrameLowering> FrameLowering;
OwningPtr<const MipsTargetLowering> TLInfo;
+...
2013 Apr 01
3
[LLVMdev] proposed change to class BasicTTI and dual mode mips16/32 working
On Thu, Mar 28, 2013 at 12:22 PM, Nadav Rotem <nrotem at apple.com> wrote:
> IMHO the right way to handle target function attributes is to
> re-initialize the target machine and TTI for every function (if the
> attributes changed). Do you have another solution in mind ?
I don't really understand this.
TargetMachine and TTI may be quite expensive to initialize. Doing so for
2012 Jul 16
3
[LLVMdev] RFC: LLVM incubation, or requirements for committing new backends
...t; + TargetOptions Options,
> + Reloc::Model RM, CodeModel::Model CM,
> + CodeGenOpt::Level OptLevel
> +)
> +:
> + LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
> + Subtarget(TT, CPU, FS),
> + DataLayout(Subtarget.getDataLayout()),
> + FrameLowering(TargetFrameLowering::StackGrowsUp,
> + Subtarget.device()->getStackAlignment(), 0),
> + IntrinsicInfo(this),
> + InstrItins(&Subtarget.getInstrItineraryData()),
> + mDump(false)
> +
> +{
> + // TLInfo uses InstrInfo so it must be initialized after.
> + if (Subtarget.device...
2014 Nov 03
8
[LLVMdev] [PATCH] Protection against stack-based memory corruption errors using SafeStack
...ss.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Target/TargetLowering.h"
+#include "llvm/Target/TargetOptions.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
+#include "llvm/Target/TargetFrameLowering.h"
+#include "llvm/Transforms/Utils/ModuleUtils.h"
+#include "llvm/Transforms/Utils/Local.h"
+#include "llvm/ADT/Triple.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/Support/Format.h"
+#include "llvm/Support/raw_os_ostream.h&quo...