Displaying 3 results from an estimated 3 matches for "getfpimm".
2011 Oct 10
2
[LLVMdev] Adding fixups and relocations late in code generation
...tOperand(OpNo);
if (MO.isReg()) {
unsigned Reg = MO.getReg();
unsigned RegNo = getMipsRegisterNumbering(Reg);
return RegNo;
} else if (MO.isImm()) {
return static_cast<unsigned>(MO.getImm());
} else if (MO.isFPImm()) {
return static_cast<unsigned>(APFloat(MO.getFPImm())
.bitcastToAPInt().getHiBits(32).getLimitedValue());
} else if (MO.isExpr()) {
const MCExpr *p_expr = MO.getExpr();
Fixups.push_back(MCFixup::Create(0, p_expr,
MCFixupKind(Mips::fixup_Mips_Branch_PCRel)));
}
return 0;
}
############################################
L...
2011 Sep 29
1
[LLVMdev] Floating-Point Constants in TableGen?
Is it possible to represent floating-point constants in TableGen
definitions?
Let's say I have the following pattern:
def : Pat<(i1 (trunc RegI16:$a)), (SETPGTu16ri RegI16:$a, 0)>;
Note the zero constant in the result. Is there a way to represent
floating-point literals in the same way? Something like...
def : Pat<(i1 (uint_to_fp RegF32:$a)), (SETPGTf32ri RegF32:$a,
2011 Oct 10
0
[LLVMdev] Adding fixups and relocations late in code generation
...gt; unsigned Reg = MO.getReg();
>
> unsigned RegNo = getMipsRegisterNumbering(Reg);
> return RegNo;
>
> } else if (MO.isImm()) {
> return static_cast<unsigned>(MO.getImm());
> } else if (MO.isFPImm()) {
> return static_cast<unsigned>(APFloat(MO.getFPImm())
> .bitcastToAPInt().getHiBits(32).getLimitedValue());
> } else if (MO.isExpr()) {
> const MCExpr *p_expr = MO.getExpr();
> Fixups.push_back(MCFixup::Create(0, p_expr,
> MCFixupKind(Mips::fixup_Mips_Branch_PCRel)));
> }
> return 0;
> }
>
> ###...