Displaying 3 results from an estimated 3 matches for "getfpcctombcc".
2017 Mar 14
2
Help understanding and lowering LLVM IDS conditional codes correctly
...is happening? It sounds like a bug we should
fix.
>
> What is ideal place where I can convert unordered comparison to un
> comparison + OR + ordered comparison ?
> Can I do it by adding required SDNodes ?
> for example I am trying to do it in LowerBR_CC as shown below:
> getFPCCtoMBCC(CC,TCC);
> TargetCC = DAG.getConstant(TCC, dl, MVT::i8);
> Flag = DAG.getNode(XXXISD::FCMP, dl, MVT::Glue, LHS, RHS,
> TargetCC);
> if (isUnordered) {
> TCC = XXX::COND_UN;
> TargetCC = DAG.getConstant(TCC, dl, MVT::i8);
>...
2017 Mar 09
2
Help understanding and lowering LLVM IDS conditional codes correctly
...O:
> CondCode = XXXCC::COND_UN;
> break;
> case ISD::SETO:
> case ISD::SETUEQ:
> case ISD::SETUGT:
> case ISD::SETUGE:
> case ISD::SETULT:
> case ISD::SETULE:
> case ISD::SETUNE:
> CC = getSetCCInverse(CC,false);
> getFPCCtoMBCC(CC,CondCode);
> break;
> }
> }
>
> I am generating wrong code when using floating point library call for
> comparions. For the following simple case:
> float branchTest(float a, float b) {
> float retVal;
> if (a == b) {
> retVal = a / b + 22.34;
> }
> r...
2017 Feb 25
2
Help understanding and lowering LLVM IDS conditional codes correctly
...dCode = XXXCC::COND_NE;
break;
case ISD::SETUO:
CondCode = XXXCC::COND_UN;
break;
case ISD::SETO:
case ISD::SETUEQ:
case ISD::SETUGT:
case ISD::SETUGE:
case ISD::SETULT:
case ISD::SETULE:
case ISD::SETUNE:
CC = getSetCCInverse(CC,false);
getFPCCtoMBCC(CC,CondCode);
break;
}
}
I am generating wrong code when using floating point library call for
comparions. For the following simple case:
float branchTest(float a, float b) {
float retVal;
if (a == b) {
retVal = a / b + 22.34;
}
return retVal;
}
I am getting:
brlid r15,__nesf2
nop
beqi r3...