search for: getfirsttermin

Hey, guys, I am creating some move instructions with MRegisterInfo::copyRegToReg. How do I get a pointer to the instruction that I just created? Is there a way to do something like: // mbb is MachineBasicBlock, reg_info is MRegisterInfo MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); reg_info->copyRegToReg(mbb, iter, dst, src, rc); iter--; (???) MachineInstr * new_move_instruction = iter; (???) This does not work though. Thank you, Fernando

...MachineFunction & mf, MachineBasicBlock & mbb, unsigned src, unsigned dst ) { MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); const TargetRegisterClass *rc = mf.getSSARegMap()->getRegClass(dst); const MRegisterInfo * reg_info = mf.getTarget().getRegisterInfo(); reg_info->copyRegToReg(mbb, iter, dst, src, rc); } But the getRegClass method seems to expect a virtual register. Could someone fix th...

MachineBasicBlock allows for multiple terminators. Unconditional branches and returns are marked as terminators; the MIPS backend also marks conditional branches as terminators. The MachineBasicBlock then has a helper function getFirstTerminator which iterates from the first terminator to the end of the MBB. So it seems to me that an MBB is a kind of superblock, single entrance and multiple side exits. There are also TailDuplication and BranchFolding passes. While these two are technically not part of the superblock definition, they a...

> On Sun, 2 Jul 2006, Fernando Magno Quintao Pereira wrote: > > > MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); > > const TargetRegisterClass *rc = mf.getSSARegMap()->getRegClass(dst); > > const MRegisterInfo * reg_info = mf.getTarget().getRegisterInfo(); > > reg_info->copyRegToReg(mbb, iter, dst, src, rc); > > } > > > > But the getRegClass method see...

On Sun, 2 Jul 2006, Fernando Magno Quintao Pereira wrote: > MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); > const TargetRegisterClass *rc = mf.getSSARegMap()->getRegClass(dst); > const MRegisterInfo * reg_info = mf.getTarget().getRegisterInfo(); > reg_info->copyRegToReg(mbb, iter, dst, src, rc); > } > > But the getRegClass method seems to expect a virtual registe...

...uys, I am creating some move instructions with > MRegisterInfo::copyRegToReg. How do I get a pointer to the instruction > that I just created? Is there a way to do something like: > > // mbb is MachineBasicBlock, reg_info is MRegisterInfo > > MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); > > reg_info->copyRegToReg(mbb, iter, dst, src, rc); > > iter--; (???) > > MachineInstr * new_move_instruction = iter; (???) > > This does not work though. > > Thank you, > > Fernando > _______________________________________________ > LLVM Develo...

...hineBasicBlock.h:153 #4 0x014e6f78 in spillAll (this=0x240d200, MI=0x241393c) at /scratch/tmp/octeon/llvm-test/source/lib/CodeGen/RegAllocFast.cpp:324 #5 0x014ed6f4 in AllocateBasicBlock (this=0x240d200) at /scratch/tmp/octeon/llvm-test/source/lib/CodeGen/RegAllocFast.cpp:1101 1. spillAll(MBB->getFirstTerminator()) at RegAllocFast.cpp:1101 is invoked. getFirstTerminator returns an end iterator here and is converted to MachineInstr* when it is passed to spillAll. 2. spillVirtReg(MI, i) at RegAllocFast.cpp:324 is invoked. constructor of MachineBasicBlock::iterator in MachineBasicBlock.cpp:152 is called a...

Thank you for your reply! > Every MachineBasicBlock has a list of successors; you can access it with > the successors() accessor. That's what you should be using for any CFG > analysis. I am aware of these methods of class MachineBasicBlock, which allows one to access a MachineBasicBlock's successors and predecessors in the CFG. But the CFG itself may no longer be valid if a

...B.begin(); // If this basic block does not contain an invoke, then control flow always // reaches the end of it, so place the copy there. The logic below works in // this case too, but is more expensive. if (!isa<InvokeInst>(MBB.getBasicBlock()->getTerminator())) return MBB.getFirstTerminator(); If the copy insn affects the status flags, then it should not be inserted between the cmp (which also affects the status flags) and the branch insn. So the above piece of code looks incorrect. - Sanjiv

...with both sides returning. There was an unrelated problem there, and while I was working on it I found out that we can still generate a basic block with a conditional return in the middle of it. This is the late if-conversion, so it may be that some rules are relaxed at this point. Still, MBB::getFirstTerminator would return the conditional return even though it may be followed by other instruction, and if it was to happen earlier in the optimization sequence, a lot of things could go wrong. It seems like this is not causing more trouble simply because there is no earlier optimization that could &q...

Hi, In PHI node elimination pass to insert the copy in the predecessor block, there is a check if terminator is not an invoke instruction then place the copy there only. However for invoke terminator instruction a safe position is located for copy insertion. My doubt is why is this safe location search done only for invoke instruction and not for other terminators such as branch.

...basic block does not contain an invoke, then control flow > always > // reaches the end of it, so place the copy there. The logic below > works in > // this case too, but is more expensive. > if (!isa<InvokeInst>(MBB.getBasicBlock()->getTerminator())) > return MBB.getFirstTerminator(); > > If the copy insn affects the status flags, then it should not be > inserted between the cmp (which also affects the status flags) and the > branch insn. > > So the above piece of code looks incorrect. Ok, there are many places in llvm codegen that insert copies. The...

Hi, again, I think I got around this problem of discovering the class of a physical register. I am using this code here: void PhiDeconstruction_Fer::add_move (MachineBasicBlock & mbb, unsigned src, unsigned dst) { MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); const MRegisterInfo * reg_info = this->machine_function->getTarget().getRegisterInfo(); // TODO: verify if does not causes incorrect allocation: for(MRegisterInfo::regclass_iterator rcii = reg_info->regclass_begin(), rcie =...

> > Thank you Chris. I will try to implement the TwoAddress pass to run on > > machine code. Why it has not been originally implemented to run on > > machine code? > > I'm not sure what you mean. It definitely does run on machine code. I was thinking that it only transformed instructions with virtual registers because of this code in the TwoAddressInstructionPass.cpp:

On Mon, 26 Jun 2006, Fernando Magno Quintao Pereira wrote: >>> Thank you Chris. I will try to implement the TwoAddress pass to run on >>> machine code. Why it has not been originally implemented to run on >>> machine code? >> >> I'm not sure what you mean. It definitely does run on machine code. > > I was thinking that it only transformed

...take a bunch of space. You'd be far better off by not throwing away the information you need earlier. -Chris > void PhiDeconstruction_Fer::add_move > (MachineBasicBlock & mbb, unsigned src, unsigned > dst) { > MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); > const MRegisterInfo * reg_info = > this->machine_function->getTarget().getRegisterInfo(); > > // TODO: verify if does not causes incorrect allocation: > for(MRegisterInfo::regclass_iterator rcii = reg_info->regclass_begin(), >...

Hello, The function ARMBaseInstrInfo::AnalyzeBranch contains the following piece of code: } else if (I->isReturn()) { // Returns can't be analyzed, but we should run cleanup. CantAnalyze = !isPredicated(I); } else { This could lead to cases where for a block that ends with a conditional return, AnalyzeBranch returns false (i.e. analyzed), both TBB and FBB are

...fter the first terminator *** > - function: main > - basic block: BB#1 entry (0x4911600) > - instruction: SUB > First terminator was: BEQ %vreg3, %ZERO, <BB#2>, %AT<imp-def>; GPR32:%vreg3 That means you inserted your instructions after the jump of the basic block. Use getFirstTerminator as insertion point. > > > 4.*** Bad machine code: Non-terminator instruction after the first terminator *** > - function: main > - basic block: BB#1 entry (0x4632600) > - instruction: SLL > First terminator was: BEQ %vreg3, %ZERO, <BB#2>, %AT<imp-def>; G...

Running llc with '-verify-machineinstrs' may tell you which instruction break the SSA form. Ruiling From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of jin chuan see via llvm-dev Sent: Monday, September 11, 2017 10:02 AM To: Matthias Braun <mbraun at apple.com> Cc: llvm-dev at lists.llvm.org Subject: Re: [llvm-dev] Live Register Spilling Sorry about the