Displaying 10 results from an estimated 10 matches for "getextload".
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g_sextload
2008 Sep 13
2
[LLVMdev] Alignment of constant loads
...e aligned to the preferred alignment, rather than the ABI
> alignment? We're not sure where this should be "fixed".
It looks like the best way to do this is to visit the handful of
places in legalize that create loads from constant pools and
add alignment parameters to the getLoad/getExtLoad calls.
If you move the handling of Alignment==0 out of ScheduleDAGEmit.cpp
and into SelectionDAG::getConstantPool, you can then have legalize
read the alignment from the node, instead of making its own
decision:
cast<ConstantPoolSDNode>(CPIdx)->getAlignment()
Dan
2008 Sep 15
0
[LLVMdev] Alignment of constant loads
Hi Dan,
> It looks like the best way to do this is to visit the handful of
> places in legalize that create loads from constant pools and
> add alignment parameters to the getLoad/getExtLoad calls.
>
> If you move the handling of Alignment==0 out of ScheduleDAGEmit.cpp
> and into SelectionDAG::getConstantPool, you can then have legalize
> read the alignment from the node, instead of making its own
> decision:
> cast<ConstantPoolSDNode>(CPIdx)->getAlignment...
2017 Sep 18
1
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...n "DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT" like this roughly.
> if (N->getOperand(0).getValueType().getVectorElementType().getSizeInBits() < 8) {
> return DAG.getLoad(N->getValueType(0), dl, Store, StackPtr, MachinePointerInfo());
> } else {
> return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr, MachinePointerInfo(), EltVT);
> }
I assume that we need the opposite -
if (.. < 8)
getExtLoad // VT should be MVT::i8, MemVT should be MVT::i1
else
getLoad
- Elena
From: jingu at codeplay.com [mailto:jingu at codeplay....
2013 Mar 04
1
[LLVMdev] Custom Lowering of ARM zero-extending loads
...ype ExtType = LD->getExtensionType();
if (LD->getExtensionType() == ISD::ZEXTLOAD) {
DEBUG(errs() << "ZEXTLOAD\n");
SDValue Chain = LD->getChain();
SDValue Ptr = LD->getBasePtr();
DebugLoc dl = Op.getNode()->getDebugLoc();
SDValue LdResult = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::i32,
Chain, Ptr, LD->getPointerInfo(),
MVT::i32,
LD->isVolatile(), LD->isNonTemporal(),
LD->getAlignment());
Chain = LdResult.getValue(1);
SDV...
2017 Sep 17
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...ize less than 8bit on "DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT" like this roughly.
if (N->getOperand(0).getValueType().getVectorElementType().getSizeInBits() < 8) {
return DAG.getLoad(N->getValueType(0), dl, Store, StackPtr, MachinePointerInfo());
} else {
return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr, MachinePointerInfo(), EltVT);
}
How do you think about it?
Thanks,
JinGu Kang
On 15/09/2017 18:42, Demikhovsky, Elena wrote:
extends the elements to 8bit and stores them on stack.
Store is responsible for zero-extend. This is the policy...
2016 Jun 04
4
Gluing arbitrary nodes together
..., AVR::SREG, MVT::i8);
// Disable interrupts (`clr` is equivalent to `bclr 7`).
auto ClearInterrupts = DAG.getNode(AVRISD::BCLR, DL, MVT::Glue,
DAG.getConstant(7, DL, MVT::i8));
// Perform the nonatomic load.
auto *Node = cast<AtomicSDNode>(AtomicOp.getNode());
SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(AtomicOp),
AtomicOp.getValueType(),
Node->getChain(), Node->getBasePtr(),
Node->getMemoryVT(), Node->getMemOperand());
auto Restore = DAG.getCopyToReg(DAG.getEntryNode(), DL, AVR::SREG, Save);
re...
2017 Sep 15
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
> extends the elements to 8bit and stores them on stack.
Store is responsible for zero-extend. This is the policy...
- Elena
-----Original Message-----
From: jingu at codeplay.com [mailto:jingu at codeplay.com]
Sent: Friday, September 15, 2017 17:45
To: llvm-dev at lists.llvm.org; Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com
Subject: Re: Question
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...T.getSizeInBits()/8,
- TLI.getPointerTy()));
- // Store the incremented VAList to the legalized pointer
- Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
- // Load the actual argument out of the pointer VAList
- Result = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Tmp3, VAList, NULL, 0, VT);
- }
- // Remember that we legalized the chain.
- AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
- break;
-
- case ISD::LOAD: {
- LoadSDNode *LD = cast<LoadSDNode>(Node);
- ISD::LoadExtType ExtType = IS...