search for: getcopyfromreg

...from the correct register class in the end. I tried mocking this up using the following. (Base is what's returned as the Ax in the move expression above when the DAG is constructed due to SelectAddr().) SDOperand chain = CurDAG->getCopyToReg(Base, M68K::A3, Base); Base = CurDAG->getCopyFromReg(chain, M68K::A3, MVT::i32); This actually generates valid, but horrible code: int deref(int *p) { return *p; } gives move.l a0, a3 -- a0 is a live in (first pointer arg) move.l (a3), d0 -- d0 is a live out (first integer return value) rts int deref(int **p) { return **p; } gives move.l a0,...

...l.com>: > > I tried mocking this up using the following. (Base is what's returned as > the Ax in the move expression above when the DAG is constructed due to > SelectAddr().) > > SDOperand chain = CurDAG->getCopyToReg(Base, M68K::A3, Base); > Base = CurDAG->getCopyFromReg(chain, M68K::A3, MVT::i32); > Replying to myself here. This worked a bit better :) const unsigned addressReg = RegMap->createVirtualRegister(&M68K::AR32RegClass); SDOperand chain = CurDAG->getCopyToReg(Base, addressReg, Base); Base = CurDAG->getCopyFromReg(chain, addr...

Dan Gohman wrote: > There certainly are wishlist items for TableGen and TableGen-based > instruction descriptions, though I don't know of an official list. > Offhand, > a few things that come to mind are the ability to handle nodes with > multiple results, Is there an official workaround, BTW? - Volodya

...ing, in particular, I attempt to create a LowerDYNAMIC_STACKALLOC function similar to the Thumb1. However, since my SP register is not part of the set of General Purpose registers, and the SP only has special instructions for it, I can NOT use the Thumb1 code implementation below: SDValue SP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32); Chain = SP.getValue(1); SP = DAG.getNode(ISD::SUB, DL, MVT::i32, SP, Size); I must use this instead: SDValue SP = DAG.getRegister(CPU74::SP, VT); SP = DAG.getNode(ISD::SUB, dl, MVT::i16, SP, Size); The ‘getCopyFromReg’ code in the first excerpt produces suboptimal...

...TargetCC); > Flag = DAG.getNode(ISD::OR, dl, MVT::Glue, Flag, UnComp); > } > but here I can't OR 2 MVT::Glue value. > How can I compare results of two fcmp SDValue objs? If your FCMP node sets some register, you'd need to read it (DAG.getCopyFromReg). -Hal > > Please provide some guidance. > > Sincerely, > Vivek > > On Thu, Mar 9, 2017 at 10:29 PM, vivek pandya <vivekvpandya at gmail.com > <mailto:vivekvpandya at gmail.com>> wrote: > > > > On Thu, Mar 9, 2017 at 9:35 PM, Hal Finkel <h...

...be kept in the // RegsToPass vector. if (VA.isRegLoc()) { RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); } else { // Sanity check. assert(VA.isMemLoc()); // Get the stack pointer if needed. if (StackPtr.getNode() == 0) { StackPtr = DAG.getCopyFromReg(Chain, dl, ARC::SP, getPointerTy()); } SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, DAG.getIntPtrConstant(VA.getLocMemOffset())); MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(),false, false, 0)); } ....

...es.h was a good hint. But there are still some things that I can't figure out: // 'mov eax, 41' Chain = DAG.getCopyToReg(Chain, DAG.getRegister(X86::EAX, MVT::i32), DAG.getConstant(41, MVT::i32), InFlag); InFlag = Chain.getValue(1); // 'inc eax' SDValue eaxVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32); SDValue inc = DAG.getNode(ISD::ADD, MVT::i32, eaxVal, DAG.getConstant(1, MVT::i32)); InFlag = SDValue(); Chain = DAG.getCopyToReg(Chain, DAG.getRegister(X86::EAX, MVT::i32), inc, InFlag); InFlag = Chain.getValue(1); This code produces the following assembly inst...

...guments() like this: .... for (auto &VA : ArgLocs) { if (VA.isRegLoc()) { // Arguments passed in registers EVT RegVT = VA.getLocVT(); VReg = RegInfo.createVirtualRegister(&FOO::BRegsRegClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); SDValue ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); SDValue ArgIn_copy = DAG.getNode(FOOISD::MOVE_FLAG , dl, MVT::i32, Chain, ArgIn); // this node is added in order to move the value from BRegs class to ARegs class and I want it be kept even it is not used later on InVals.push_back(ArgIn_copy); } } After c...

...It's IR from the front-end is: ... ;<label>:3 store i16 1, i16 *a, align 2 br label %5 ;<label>:4 store i16 0, i16 *a, align 2 br label %5 ;<label>:5 %6 = load i16 *a, align 2 store i16 %6, i16 c I used getCopyToReg in SelectionDAG for store instruction to store value, and getCopyFromReg for load instruction. So, storage values in block '<label>:3' and '<label>:4' are stored in VR0 and VR1 respectively. However, load instruction in block '<label>:5' cannot choose which register should be read. Can anybody give an idea to overcome such a cas...

...it fails the assertion `ResNo < NumValues && "Illegal result number!"'. More specifically I am doing something like: EVT ReturnValueVT = Node->getValueType(0) ; SDValue ChainIn = Node->getOperand(0); SDValue Zero = CurDAG->getCopyFromReg(ChainIn, DL, Mips::ZERO, MVT::i32); SDValue op0 = Node->getOperand(2); SDValue op1 = Node->getOperand(3); SDValue op2= Node->getOperand(4); SDValue op3 = Node->getOperand(5); SDValue Ops[]= { op0, op1, op2, op3, Zero...

On Jul 1, 2009, at 2:22 PMPDT, Dan Gohman wrote: >> Ops.push_back(DAG.getConstant(1, MVT::i32)); >> Chain = DAG.getNode(ISD::ADD, DAG.getVTList(MVT::Other, MVT::i32), >> &Ops[0], Ops.size()); >> >> Isn't that the way how it is supposed to work? > > ADD does not use a chain, so there's no chain operand, or > MVT::Other result for it in an ADD

Thanks, that sounds like it would work. Was this based on what any other target did? Or do any other targets take this approach? I just want to make sure that we don't already have a hook suitable for this. Overriding runOnFunction to run what could be described as just a "late SelectionDAG pass" sounds pretty intrusive. Do you remember other approaches that didn't work? --

Hi Andrew, Thank you for the suggestion. I've looked at CodeGenPrepare.cpp and MoveExtToFormExtLoad() is never run. I also notice that the ARM target produces the same additional register usage (copy) and zero extending (of the copy). (See the usage of r3 &r5 and also r12 & r4 in attached file arm-strcspn.s, my understanding is that 'ldrb' is zero extending.) Here is a

...:RSP). d. Setting the value of the node to RAX in LowerDYNAMIC_STACKALLOC, making the last part of the function effectively look like this: // Reg is RAX or EAX, based on the subtarget Chain = DAG.getNode(X86ISD::SEG_ALLOCA, dl, NodeTys, Chain, Flag); Flag = Chain.getValue(1); Chain = DAG.getCopyFromReg(Chain, dl, Reg, SPTy).getValue(1); SDValue Ops1[2] = { Chain.getValue(0), Chain }; return DAG.getMergeValues(Ops1, 2, dl); Firstly, I would also like some feedback on this implementation in general. Secondly, the problem I'm facing: in the final assembly generated, the move instruction t...

...Op1, Op2), 0); // Copy the low half of the result, if it is needed. if (!SDValue(N, 0).use_empty()) { SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, LoReg, NVT, InFlag); InFlag...

...ck in %rax for > functions returning large structures. We certainly could do the same > with %ah, but what IR would we generate to fetch that value in the body > of a routine? It would almost certainly be an @llvm.whatever intrinsic call at the IR level with custom SDAG lowering that uses getCopyFromReg to copy the value back out of the stashed VReg you found before. > We haven't created our own private OpenVMS calling convention but just > riding along on the standard convention. Another thought would be to > create a new CC but that seems overkill just for this. That sounds prett...

On Sep 9, 2010, at 12:59 PM, Borja Ferrer wrote: > Hello, i've noticed a new possible missed optimization while testing more trivial code. > This time it's not a with a xor but with a multiplication instruction and the example is little bit more involved. > > C code: > > typedef short t; > t foo(t a, t b) > { > t a4 = a*b; > return a4; > } >

...s, CC_FOO); for (auto &VA : ArgLocs) { if (VA.isRegLoc()) { // Arguments passed in registers EVT RegVT = VA.getLocVT(); const unsigned VReg = RegInfo.createVirtualRegister(&FOO::PRegsRegClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); SDValue ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); InVals.push_back(ArgIn); continue; } // assume the parameter registers are enough, no need to store in frame right now } return Chain; } In the above function, CC_FOO is defined in CallingConv.td and "CCIfType<[i32], CCAssignToReg<[P0,P1...

On Sep 10, 2013, at 8:59 AM, Robert Lytton <robert at xmos.com> wrote: > Hi, > > A bit more information. > I believe my problem lies with the fact that the load is left as 'anyext from i8'. > On the XCore target we know this will become an 8bit zext load - as there is no 8bit sign extended load! > If BB#1 were to force the load to a "zext from i8" would

As part of our OpenVMS-specific changes, we're adding an arg-count to all of our calls. We've done this as part of callLowering to put the # of slots used into %ah and leaving %al to hold the standard info about vector registers.  That part is working. However, we're struggling somewhat on the code in the prologue to capture the %ah value to then be obtained by our