search for: getconstantfp

...lt;ConstantFPSDNode>(N2.getNode()); if (N1CFP) { @@ -3415,28 +3416,32 @@ switch (Opcode) { case ISD::FADD: s = V1.add(V2, APFloat::rmNearestTiesToEven); - if (s != APFloat::opInvalidOp) + if (!HasFPExceptions || s != APFloat::opInvalidOp) return getConstantFP(V1, VT); break; case ISD::FSUB: s = V1.subtract(V2, APFloat::rmNearestTiesToEven); - if (s!=APFloat::opInvalidOp) + if (!HasFPExceptions || s!=APFloat::opInvalidOp) return getConstantFP(V1, VT); break; case ISD::FMUL: s = V1...

...> @@ -3415,28 +3416,32 @@ >> switch (Opcode) { >> case ISD::FADD: >> s = V1.add(V2, APFloat::rmNearestTiesToEven); >> - if (s != APFloat::opInvalidOp) >> + if (!HasFPExceptions || s != APFloat::opInvalidOp) >> return getConstantFP(V1, VT); >> break; >> case ISD::FSUB: >> s = V1.subtract(V2, APFloat::rmNearestTiesToEven); >> - if (s!=APFloat::opInvalidOp) >> + if (!HasFPExceptions || s!=APFloat::opInvalidOp) >> return getConstantFP(V1, VT); >...

...tore is volatile, this transform must not increase // the number of stores. For example, on x86-32 an f64 can be stored in one // processor operation but an i64 (which is not legal) requires two. So the // transform should not be done in this case. if (Value.getOpcode() != ISD::TargetConstantFP) { SDValue Tmp; switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { default: llvm_unreachable("Unknown FP type"); case MVT::f80: // We don't do this for these yet. case MVT::f128: case MVT::ppcf128: break; case MVT::f32:...

Hi Sanjay, Thanks, I saw this flag and it's definitely should be considered, but it appeared to me to be static characteristic of target platform. I'm not sure how appropriate it would be to change its value from a front-end. It says "Has", while optional flag would rather say "Uses" meaning that implementation cares about floating point exceptions. Regards, Sergey

...AG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, switch (Opcode) { case ISD::FADD: s = V1.add(V2, APFloat::rmNearestTiesToEven); - if (!HasFPExceptions || s != APFloat::opInvalidOp) + if (isSafeToOptimizeFPOp(s, APFloat::opInvalidOp)) return getConstantFP(V1, VT); break; case ISD::FSUB: s = V1.subtract(V2, APFloat::rmNearestTiesToEven); - if (!HasFPExceptions || s!=APFloat::opInvalidOp) + if (isSafeToOptimizeFPOp(s, APFloat::opInvalidOp)) return getConstantFP(V1, VT); break; case ISD:...

...tValueType(); EVT NVT = Node->getValueType(0); APFloat apf(DAG.EVTToAPFloatSemantics(VT), APInt::getNullValue(VT.getSizeInBits())); APInt x = APInt::getSignBit(NVT.getSizeInBits()); (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); Tmp1 = DAG.getConstantFP(apf, dl, VT); Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT), Node->getOperand(0), Tmp1, ISD::SETLT); True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); // TODO: Should any fast-math-flags be set for the FSUB? Fal...

...); > > APFloat apf(DAG.EVTToAPFloatSemantics(VT), > > APInt::getNullValue(VT.getSizeInBits())); > > APInt x = APInt::getSignMask(NVT.getSizeInBits()); > > (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); > > Tmp1 = DAG.getConstantFP(apf, dl, VT); > > Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT), > > Node->getOperand(0), > > Tmp1, ISD::SETLT); > > True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); > > // TODO: Shoul...

On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more

On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant

...and(j); + } + + Op = DAG.getNode(Op.getOpcode(), dl, NVT, &Operands[0], Operands.size()); + + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Op); +} + +SDValue VectorLegalizer::ExpandFNEG(SDValue Op) { + if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) { + SDValue Zero = DAG.getConstantFP(-0.0, Op.getValueType()); + return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), + Zero, Op.getOperand(0)); + } + return UnrollVectorOp(Op); +} + +SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) { + MVT VT = Op.getValueType(); + unsigned NumElems = VT.ge...

Sounds like the select lowering issue is definitely separate from the FENV work. Is there a bug report with a C or IR example? You want to generate compare and branch instead of a cmov for something like this? int foo(float x) { if (x < 42.0f) return x; return 12; } define i32 @foo(float %x) { %cmp = fcmp olt float %x, 4.200000e+01 %conv = fptosi float %x to i32 %ret = select

...1 - a) * c) > +SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op, > + SelectionDAG &DAG) const > +{ > + DebugLoc DL = Op.getDebugLoc(); > + EVT VT = Op.getValueType(); > + SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT, > + DAG.getConstantFP(1.0f, MVT::f32), > + Op.getOperand(1)); > + SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA, > + Op.getOperand(3)); > + return DAG.getNode(AMDILISD::MAD, DL, VT, Op.getOperand(1), > +...

> This seems like it was done for perf reason (mispredict). Conditional-to-cmov transformation should keep > from introducing additional observable side-effects, and it's clear that whatever did this did not account > for floating point exception. That’s a very reasonable statement, but I’m not sure it corresponds to the way we have typically approached this sort of problem. In