Displaying 8 results from an estimated 8 matches for "getcondcodeact".
2012 Jul 26
2
[LLVMdev] Why is this assertion here?
I'm trying to understand why this assertion is here.
LegalizeAction
getCondCodeAction(ISD::CondCode CC, EVT VT) const {
assert((unsigned)CC < array_lengthof(CondCodeActions) &&
(unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 &&
"Table isn't big enough!");
LegalizeAction Action = (LegalizeAction)...
2012 Jul 26
2
[LLVMdev] RFC: CondCodeActions refactor (was RE: Why is this assertion here?)
..."Table isn't big enough!");
> CondCodeActions[(unsigned)CC][VT.SimplyTy >> 5] &=
> ~(uint64_t(3UL) << (VT.SimpleTy - 32)*2);
> CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5] |= (uint64_t)Action
> << (VT.SimpleTy - 32)*2; }
>
> getCondCodeAction then becomes:
> LegalizeAction
> getCondCodeAction(ISD::CondCode CC, EVT VT) const {
> assert((unsigned)CC < array_lengthof(CondCodeActions) &&
> (unsigned)VT.getSimpleVT().SimpleTy <
> MVT::LAST_VECTOR_VALUETYPE && "Table isn't big...
2012 Jul 26
0
[LLVMdev] RFC: CondCodeActions refactor (was RE: Why is this assertion here?)
...ctions) &&
"Table isn't big enough!");
CondCodeActions[(unsigned)CC][VT.SimplyTy >> 5] &= ~(uint64_t(3UL) << (VT.SimpleTy - 32)*2);
CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5] |= (uint64_t)Action << (VT.SimpleTy - 32)*2;
}
getCondCodeAction then becomes:
LegalizeAction
getCondCodeAction(ISD::CondCode CC, EVT VT) const {
assert((unsigned)CC < array_lengthof(CondCodeActions) &&
(unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VECTOR_VALUETYPE &&
"Table isn't big enough!")...
2012 Jul 26
0
[LLVMdev] RFC: CondCodeActions refactor (was RE: Why is this assertion here?)
...ig enough!");
> > CondCodeActions[(unsigned)CC][VT.SimplyTy >> 5] &=
> > ~(uint64_t(3UL) << (VT.SimpleTy - 32)*2);
> > CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5] |= (uint64_t)Action <<
> > (VT.SimpleTy - 32)*2; }
> >
> > getCondCodeAction then becomes:
> > LegalizeAction
> > getCondCodeAction(ISD::CondCode CC, EVT VT) const {
> > assert((unsigned)CC < array_lengthof(CondCodeActions) &&
> > (unsigned)VT.getSimpleVT().SimpleTy <
> > MVT::LAST_VECTOR_VALUETYPE && &...
2012 Dec 03
2
[LLVMdev] [RFC] Replacing EVT:s with MVT:s (when possible)
...e me this list of (member) functions, taking an EVT parameter, that asserts if the argument is not an MVT:
getRegClassFor, getRepRegClassFor, getRepRegClassCostFor, setTypeAction, getLoadExtAction, isLoadExtLegal, getTruncStoreAction, isTruncStoreLegal, getIndexedLoadAction, getIndexedStoreAction, getCondCodeAction, getTypeToPromoteTo, addRegisterClass
Regards,
Patrik Hägglund
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2012 Dec 06
0
[LLVMdev] [PATCH] Replacing EVT:s with MVT:s (when possible)
...| 3 ++-
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 4 ++--
3 files changed, 9 insertions(+), 9 deletions(-)
commit 6e468d9ec25353935c96c78a717e48cb6ace6206
Author: Patrik Hägglund <patrik.h.hagglund at ericsson.com>
Date: Tue Dec 4 16:28:34 2012 +0100
Change TargetLowering::getCondCodeAction to take an MVT, instead of
EVT.
include/llvm/Target/TargetLowering.h | 12 ++++++------
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 4 ++--
lib/CodeGen/SelectionDAG/TargetLowering.cpp | 4 ++--
3 files changed, 10 insertions(+), 10 deletions(-)
commit 0a642d363069fb95a4bdaec598a1d7...
2012 Dec 03
0
[LLVMdev] [RFC] Replacing EVT:s with MVT:s (when possible)
...ist of (member) functions, taking an EVT parameter, that asserts if the argument is not an MVT:
>
> getRegClassFor, getRepRegClassFor, getRepRegClassCostFor, setTypeAction, getLoadExtAction, isLoadExtLegal, getTruncStoreAction, isTruncStoreLegal, getIndexedLoadAction, getIndexedStoreAction, getCondCodeAction, getTypeToPromoteTo, addRegisterClass
>
Please do. MVT is cheaper than EVT and conceptually cleaner when dealing with physical machine types. EVT should only be used in parts of the code generator that are "pre-legalization" because they can represent arbitrary IR types. Anyth...
2012 May 25
3
[LLVMdev] Predicate registers/condition codes question
On Thu, May 24, 2012 at 5:40 PM, Sebastian Pop <spop at codeaurora.org> wrote:
> On Thu, May 24, 2012 at 5:06 PM, Hal Finkel <hfinkel at anl.gov> wrote:
>> Sebastian,
>>
>> First, it might be useful to look at what is done in the PowerPC
>> backend. PPC also has condition registers that are larger than the
>> 1-bit conditional results, and it defines